source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iox32d3.h @ 4837

Last change on this file since 4837 was 4837, checked in by daduve, 3 years ago

Adding new version

File size: 226.6 KB
Line 
1/*****************************************************************************
2 *
3 * Copyright (C) 2016 Atmel Corporation
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 *   notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 *   notice, this list of conditions and the following disclaimer in
14 *   the documentation and/or other materials provided with the
15 *   distribution.
16 *
17 * * Neither the name of the copyright holders nor the names of
18 *   contributors may be used to endorse or promote products derived
19 *   from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 ****************************************************************************/
33
34
35#ifndef _AVR_IO_H_
36#  error "Include <avr/io.h> instead of this file."
37#endif
38
39#ifndef _AVR_IOXXX_H_
40#  define _AVR_IOXXX_H_ "iox32d3.h"
41#else
42#  error "Attempt to include more than one <avr/ioXXX.h> file."
43#endif
44
45#ifndef _AVR_ATXMEGA32D3_H_INCLUDED
46#define _AVR_ATXMEGA32D3_H_INCLUDED
47
48/* Ungrouped common registers */
49#define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
50#define GPIOR1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
51#define GPIOR2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
52#define GPIOR3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
53
54/* Deprecated */
55#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
56#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
57#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
58#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
59
60#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
61#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
62#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
63#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
64#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
65#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
66#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
67#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
68#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
69
70/* C Language Only */
71#if !defined (__ASSEMBLER__)
72
73#include <stdint.h>
74
75typedef volatile uint8_t register8_t;
76typedef volatile uint16_t register16_t;
77typedef volatile uint32_t register32_t;
78
79
80#ifdef _WORDREGISTER
81#undef _WORDREGISTER
82#endif
83#define _WORDREGISTER(regname)   \
84    __extension__ union \
85    { \
86        register16_t regname; \
87        struct \
88        { \
89            register8_t regname ## L; \
90            register8_t regname ## H; \
91        }; \
92    }
93
94#ifdef _DWORDREGISTER
95#undef _DWORDREGISTER
96#endif
97#define _DWORDREGISTER(regname)  \
98    __extension__ union \
99    { \
100        register32_t regname; \
101        struct \
102        { \
103            register8_t regname ## 0; \
104            register8_t regname ## 1; \
105            register8_t regname ## 2; \
106            register8_t regname ## 3; \
107        }; \
108    }
109
110
111/*
112==========================================================================
113IO Module Structures
114==========================================================================
115*/
116
117
118/*
119--------------------------------------------------------------------------
120XOCD - On-Chip Debug System
121--------------------------------------------------------------------------
122*/
123
124/* On-Chip Debug System */
125typedef struct OCD_struct
126{
127    register8_t OCDR0;  /* OCD Register 0 */
128    register8_t OCDR1;  /* OCD Register 1 */
129} OCD_t;
130
131
132/*
133--------------------------------------------------------------------------
134CPU - CPU
135--------------------------------------------------------------------------
136*/
137
138/* CCP signatures */
139typedef enum CCP_enum
140{
141    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
142    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
143} CCP_t;
144
145
146/*
147--------------------------------------------------------------------------
148CLK - Clock System
149--------------------------------------------------------------------------
150*/
151
152/* Clock System */
153typedef struct CLK_struct
154{
155    register8_t CTRL;  /* Control Register */
156    register8_t PSCTRL;  /* Prescaler Control Register */
157    register8_t LOCK;  /* Lock register */
158    register8_t RTCCTRL;  /* RTC Control Register */
159    register8_t reserved_0x04;
160} CLK_t;
161
162
163/* Power Reduction */
164typedef struct PR_struct
165{
166    register8_t PRGEN;  /* General Power Reduction */
167    register8_t PRPA;  /* Power Reduction Port A */
168    register8_t reserved_0x02;
169    register8_t PRPC;  /* Power Reduction Port C */
170    register8_t PRPD;  /* Power Reduction Port D */
171    register8_t PRPE;  /* Power Reduction Port E */
172    register8_t PRPF;  /* Power Reduction Port F */
173} PR_t;
174
175/* System Clock Selection */
176typedef enum CLK_SCLKSEL_enum
177{
178    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2 MHz RC Oscillator */
179    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32 MHz RC Oscillator */
180    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32.768 kHz RC Oscillator */
181    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
182    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
183} CLK_SCLKSEL_t;
184
185/* Prescaler A Division Factor */
186typedef enum CLK_PSADIV_enum
187{
188    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
189    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
190    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
191    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
192    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
193    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
194    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
195    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
196    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
197    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
198} CLK_PSADIV_t;
199
200/* Prescaler B and C Division Factor */
201typedef enum CLK_PSBCDIV_enum
202{
203    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
204    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
205    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
206    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
207} CLK_PSBCDIV_t;
208
209/* RTC Clock Source */
210typedef enum CLK_RTCSRC_enum
211{
212    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1 kHz from internal 32kHz ULP */
213    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
214    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1.024 kHz from 32.768 kHz internal oscillator */
215    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
216    CLK_RTCSRC_RCOSC32_gc = (0x06<<1),  /* 32.768 kHz from 32.768 kHz internal oscillator */
217    CLK_RTCSRC_EXTCLK_gc = (0x07<<1),  /* External Clock from TOSC1 */
218} CLK_RTCSRC_t;
219
220
221/*
222--------------------------------------------------------------------------
223SLEEP - Sleep Controller
224--------------------------------------------------------------------------
225*/
226
227/* Sleep Controller */
228typedef struct SLEEP_struct
229{
230    register8_t CTRL;  /* Control Register */
231} SLEEP_t;
232
233/* Sleep Mode */
234typedef enum SLEEP_SMODE_enum
235{
236    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
237    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
238    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
239    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
240    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
241} SLEEP_SMODE_t;
242
243
244
245#define SLEEP_MODE_IDLE (0x00<<1)
246#define SLEEP_MODE_PWR_DOWN (0x02<<1)
247#define SLEEP_MODE_PWR_SAVE (0x03<<1)
248#define SLEEP_MODE_STANDBY (0x06<<1)
249#define SLEEP_MODE_EXT_STANDBY (0x07<<1)
250/*
251--------------------------------------------------------------------------
252OSC - Oscillator
253--------------------------------------------------------------------------
254*/
255
256/* Oscillator */
257typedef struct OSC_struct
258{
259    register8_t CTRL;  /* Control Register */
260    register8_t STATUS;  /* Status Register */
261    register8_t XOSCCTRL;  /* External Oscillator Control Register */
262    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
263    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
264    register8_t PLLCTRL;  /* PLL Control REgister */
265    register8_t DFLLCTRL;  /* DFLL Control Register */
266} OSC_t;
267
268/* Oscillator Frequency Range */
269typedef enum OSC_FRQRANGE_enum
270{
271    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
272    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
273    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
274    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
275} OSC_FRQRANGE_t;
276
277/* External Oscillator Selection and Startup Time */
278typedef enum OSC_XOSCSEL_enum
279{
280    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
281    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
282    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
283    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
284    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
285} OSC_XOSCSEL_t;
286
287/* PLL Clock Source */
288typedef enum OSC_PLLSRC_enum
289{
290    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
291    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
292    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
293} OSC_PLLSRC_t;
294
295
296/*
297--------------------------------------------------------------------------
298DFLL - DFLL
299--------------------------------------------------------------------------
300*/
301
302/* DFLL */
303typedef struct DFLL_struct
304{
305    register8_t CTRL;  /* Control Register */
306    register8_t reserved_0x01;
307    register8_t CALA;  /* Calibration Register A */
308    register8_t CALB;  /* Calibration Register B */
309    register8_t COMP0;  /* Oscillator Compare Register 0 */
310    register8_t COMP1;  /* Oscillator Compare Register 1 */
311    register8_t COMP2;  /* Oscillator Compare Register 2 */
312    register8_t reserved_0x07;
313} DFLL_t;
314
315
316/*
317--------------------------------------------------------------------------
318RST - Reset
319--------------------------------------------------------------------------
320*/
321
322/* Reset */
323typedef struct RST_struct
324{
325    register8_t STATUS;  /* Status Register */
326    register8_t CTRL;  /* Control Register */
327} RST_t;
328
329
330/*
331--------------------------------------------------------------------------
332WDT - Watch-Dog Timer
333--------------------------------------------------------------------------
334*/
335
336/* Watch-Dog Timer */
337typedef struct WDT_struct
338{
339    register8_t CTRL;  /* Control */
340    register8_t WINCTRL;  /* Windowed Mode Control */
341    register8_t STATUS;  /* Status */
342} WDT_t;
343
344/* Period setting */
345typedef enum WDT_PER_enum
346{
347    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
348    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
349    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
350    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
351    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
352    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
353    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
354    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
355    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
356    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
357    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
358} WDT_PER_t;
359
360/* Closed window period */
361typedef enum WDT_WPER_enum
362{
363    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
364    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
365    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
366    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
367    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.128s @ 3.3V) */
368    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.256s @ 3.3V) */
369    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.512s @ 3.3V) */
370    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
371    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
372    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
373    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
374} WDT_WPER_t;
375
376
377/*
378--------------------------------------------------------------------------
379MCU - MCU Control
380--------------------------------------------------------------------------
381*/
382
383/* MCU Control */
384typedef struct MCU_struct
385{
386    register8_t DEVID0;  /* Device ID byte 0 */
387    register8_t DEVID1;  /* Device ID byte 1 */
388    register8_t DEVID2;  /* Device ID byte 2 */
389    register8_t REVID;  /* Revision ID */
390    register8_t JTAGUID;  /* JTAG User ID */
391    register8_t reserved_0x05;
392    register8_t MCUCR;  /* MCU Control */
393    register8_t reserved_0x07;
394    register8_t EVSYSLOCK;  /* Event System Lock */
395    register8_t AWEXLOCK;  /* AWEX Lock */
396    register8_t reserved_0x0A;
397    register8_t reserved_0x0B;
398} MCU_t;
399
400
401/*
402--------------------------------------------------------------------------
403PMIC - Programmable Multi-level Interrupt Controller
404--------------------------------------------------------------------------
405*/
406
407/* Programmable Multi-level Interrupt Controller */
408typedef struct PMIC_struct
409{
410    register8_t STATUS;  /* Status Register */
411    register8_t INTPRI;  /* Interrupt Priority */
412    register8_t CTRL;  /* Control Register */
413    register8_t reserved_0x03;
414    register8_t reserved_0x04;
415    register8_t reserved_0x05;
416    register8_t reserved_0x06;
417    register8_t reserved_0x07;
418    register8_t reserved_0x08;
419    register8_t reserved_0x09;
420    register8_t reserved_0x0A;
421    register8_t reserved_0x0B;
422    register8_t reserved_0x0C;
423    register8_t reserved_0x0D;
424    register8_t reserved_0x0E;
425    register8_t reserved_0x0F;
426} PMIC_t;
427
428
429/*
430--------------------------------------------------------------------------
431CRC - Cyclic Redundancy Checker
432--------------------------------------------------------------------------
433*/
434
435/* Cyclic Redundancy Checker */
436typedef struct CRC_struct
437{
438    register8_t CTRL;  /* Control Register */
439    register8_t STATUS;  /* Status Register */
440    register8_t reserved_0x02;
441    register8_t DATAIN;  /* Data Input */
442    register8_t CHECKSUM0;  /* Checksum byte 0 */
443    register8_t CHECKSUM1;  /* Checksum byte 1 */
444    register8_t CHECKSUM2;  /* Checksum byte 2 */
445    register8_t CHECKSUM3;  /* Checksum byte 3 */
446} CRC_t;
447
448/* Reset */
449typedef enum CRC_RESET_enum
450{
451    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
452    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
453    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
454} CRC_RESET_t;
455
456/* Input Source */
457typedef enum CRC_SOURCE_enum
458{
459    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* Disabled */
460    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
461    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
462} CRC_SOURCE_t;
463
464
465/*
466--------------------------------------------------------------------------
467EVSYS - Event System
468--------------------------------------------------------------------------
469*/
470
471/* Event System */
472typedef struct EVSYS_struct
473{
474    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
475    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
476    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
477    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
478    register8_t reserved_0x04;
479    register8_t reserved_0x05;
480    register8_t reserved_0x06;
481    register8_t reserved_0x07;
482    register8_t CH0CTRL;  /* Channel 0 Control Register */
483    register8_t CH1CTRL;  /* Channel 1 Control Register */
484    register8_t CH2CTRL;  /* Channel 2 Control Register */
485    register8_t CH3CTRL;  /* Channel 3 Control Register */
486    register8_t reserved_0x0C;
487    register8_t reserved_0x0D;
488    register8_t reserved_0x0E;
489    register8_t reserved_0x0F;
490    register8_t STROBE;  /* Event Strobe */
491    register8_t DATA;  /* Event Data */
492} EVSYS_t;
493
494/* Quadrature Decoder Index Recognition Mode */
495typedef enum EVSYS_QDIRM_enum
496{
497    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
498    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
499    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
500    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
501} EVSYS_QDIRM_t;
502
503/* Digital filter coefficient */
504typedef enum EVSYS_DIGFILT_enum
505{
506    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
507    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
508    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
509    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
510    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
511    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
512    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
513    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
514} EVSYS_DIGFILT_t;
515
516/* Event Channel multiplexer input selection */
517typedef enum EVSYS_CHMUX_enum
518{
519    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
520    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
521    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
522    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
523    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
524    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
525    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
526    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
527    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
528    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
529    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
530    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
531    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
532    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
533    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
534    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
535    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
536    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
537    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
538    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
539    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
540    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
541    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
542    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
543    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
544    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
545    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
546    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
547    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
548    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
549    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
550    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
551    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
552    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
553    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
554    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
555    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
556    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
557    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
558    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
559    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
560    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
561    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
562    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
563    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
564    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
565    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
566    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
567    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
568    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
569    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
570    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
571    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
572    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
573    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
574    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
575    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
576    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
577    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
578    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
579    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
580    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
581    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
582    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
583    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
584    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
585    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
586    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
587    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
588    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
589    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
590    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
591    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
592    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
593    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
594    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
595    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
596    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
597    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
598    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
599    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
600    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
601    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
602    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
603    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
604    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
605    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
606    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
607    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
608    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
609    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
610    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
611    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
612    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
613    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
614    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
615    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
616    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
617    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
618} EVSYS_CHMUX_t;
619
620
621/*
622--------------------------------------------------------------------------
623NVM - Non Volatile Memory Controller
624--------------------------------------------------------------------------
625*/
626
627/* Non-volatile Memory Controller */
628typedef struct NVM_struct
629{
630    register8_t ADDR0;  /* Address Register 0 */
631    register8_t ADDR1;  /* Address Register 1 */
632    register8_t ADDR2;  /* Address Register 2 */
633    register8_t reserved_0x03;
634    register8_t DATA0;  /* Data Register 0 */
635    register8_t DATA1;  /* Data Register 1 */
636    register8_t DATA2;  /* Data Register 2 */
637    register8_t reserved_0x07;
638    register8_t reserved_0x08;
639    register8_t reserved_0x09;
640    register8_t CMD;  /* Command */
641    register8_t CTRLA;  /* Control Register A */
642    register8_t CTRLB;  /* Control Register B */
643    register8_t INTCTRL;  /* Interrupt Control */
644    register8_t reserved_0x0E;
645    register8_t STATUS;  /* Status */
646    register8_t LOCK_BITS;  /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */
647} NVM_t;
648
649
650/* Lock Bits */
651typedef struct NVM_LOCKBITS_struct
652{
653    register8_t LOCK_BITS;  /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */
654} NVM_LOCKBITS_t;
655
656
657/* Fuses */
658typedef struct NVM_FUSES_struct
659{
660    register8_t reserved_0x00;
661    register8_t FUSEBYTE1;  /* Watchdog Configuration */
662    register8_t FUSEBYTE2;  /* Reset Configuration */
663    register8_t reserved_0x03;
664    register8_t FUSEBYTE4;  /* Start-up Configuration */
665    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
666} NVM_FUSES_t;
667
668
669/* Production Signatures */
670typedef struct NVM_PROD_SIGNATURES_struct
671{
672    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
673    register8_t reserved_0x01;
674    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
675    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
676    register8_t reserved_0x04;
677    register8_t reserved_0x05;
678    register8_t reserved_0x06;
679    register8_t reserved_0x07;
680    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
681    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
682    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
683    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
684    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
685    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
686    register8_t reserved_0x0E;
687    register8_t reserved_0x0F;
688    register8_t WAFNUM;  /* Wafer Number */
689    register8_t reserved_0x11;
690    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
691    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
692    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
693    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
694    register8_t reserved_0x16;
695    register8_t reserved_0x17;
696    register8_t reserved_0x18;
697    register8_t reserved_0x19;
698    register8_t reserved_0x1A;
699    register8_t reserved_0x1B;
700    register8_t reserved_0x1C;
701    register8_t reserved_0x1D;
702    register8_t reserved_0x1E;
703    register8_t reserved_0x1F;
704    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
705    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
706    register8_t reserved_0x22;
707    register8_t reserved_0x23;
708    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
709    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
710    register8_t reserved_0x26;
711    register8_t reserved_0x27;
712    register8_t reserved_0x28;
713    register8_t reserved_0x29;
714    register8_t reserved_0x2A;
715    register8_t reserved_0x2B;
716    register8_t reserved_0x2C;
717    register8_t reserved_0x2D;
718    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
719    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
720    register8_t reserved_0x30;
721    register8_t reserved_0x31;
722    register8_t reserved_0x32;
723    register8_t reserved_0x33;
724    register8_t reserved_0x34;
725    register8_t reserved_0x35;
726    register8_t reserved_0x36;
727    register8_t reserved_0x37;
728    register8_t reserved_0x38;
729    register8_t reserved_0x39;
730    register8_t reserved_0x3A;
731    register8_t reserved_0x3B;
732    register8_t reserved_0x3C;
733    register8_t reserved_0x3D;
734    register8_t reserved_0x3E;
735} NVM_PROD_SIGNATURES_t;
736
737/* NVM Command */
738typedef enum NVM_CMD_enum
739{
740    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
741    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
742    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
743    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
744    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
745    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
746    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
747    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
748    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
749    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
750    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
751    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
752    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
753    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
754    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
755    NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0),  /* Erase Flash page */
756    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
757    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
758    NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0),  /* Write Flash page */
759    NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0),  /* Erase and Write Flash page */
760    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
761    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
762    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
763    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
764    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
765    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
766    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
767    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
768    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
769} NVM_CMD_t;
770
771/* SPM ready interrupt level */
772typedef enum NVM_SPMLVL_enum
773{
774    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
775    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
776    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
777    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
778} NVM_SPMLVL_t;
779
780/* EEPROM ready interrupt level */
781typedef enum NVM_EELVL_enum
782{
783    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
784    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
785    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
786    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
787} NVM_EELVL_t;
788
789/* Boot lock bits - boot setcion */
790typedef enum NVM_BLBB_enum
791{
792    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
793    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
794    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
795    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
796} NVM_BLBB_t;
797
798/* Boot lock bits - application section */
799typedef enum NVM_BLBA_enum
800{
801    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
802    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
803    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
804    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
805} NVM_BLBA_t;
806
807/* Boot lock bits - application table section */
808typedef enum NVM_BLBAT_enum
809{
810    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
811    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
812    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
813    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
814} NVM_BLBAT_t;
815
816/* Lock bits */
817typedef enum NVM_LB_enum
818{
819    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
820    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
821    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
822} NVM_LB_t;
823
824/* Boot Loader Section Reset Vector */
825typedef enum BOOTRST_enum
826{
827    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
828    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
829} BOOTRST_t;
830
831/* 32.768kHz Timer Oscillator Pin Selection */
832typedef enum TOSCSEL_enum
833{
834    TOSCSEL_ALTERNATE_gc = (0x00<<5),  /* TOSC1/2 on separate pins */
835    TOSCSEL_XTAL_gc = (0x01<<5),  /* TOSC1/2 shared with XTAL */
836} TOSCSEL_t;
837
838/* BOD operation */
839typedef enum BOD_enum
840{
841    BOD_INSAMPLEDMODE_gc = (0x01<<4),  /* BOD enabled in sampled mode */
842    BOD_CONTINOUSLY_gc = (0x02<<4),  /* BOD enabled continuously */
843    BOD_DISABLED_gc = (0x03<<4),  /* BOD Disabled */
844} BOD_t;
845
846/* Watchdog (Window) Timeout Period */
847typedef enum WD_enum
848{
849    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
850    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
851    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
852    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
853    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
854    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
855    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
856    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
857    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
858    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
859    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
860} WD_t;
861
862/* Start-up Time */
863typedef enum SUT_enum
864{
865    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
866    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
867    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
868} SUT_t;
869
870/* Brownout Detection Voltage Level */
871typedef enum BODLVL_enum
872{
873    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
874    BODLVL_1V8_gc = (0x06<<0),  /* 1.8 V */
875    BODLVL_2V0_gc = (0x05<<0),  /* 2.0 V */
876    BODLVL_2V2_gc = (0x04<<0),  /* 2.2 V */
877    BODLVL_2V4_gc = (0x03<<0),  /* 2.4 V */
878    BODLVL_2V6_gc = (0x02<<0),  /* 2.6 V */
879    BODLVL_2V8_gc = (0x01<<0),  /* 2.8 V */
880    BODLVL_3V0_gc = (0x00<<0),  /* 3.0 V */
881} BODLVL_t;
882
883
884/*
885--------------------------------------------------------------------------
886AC - Analog Comparator
887--------------------------------------------------------------------------
888*/
889
890/* Analog Comparator */
891typedef struct AC_struct
892{
893    register8_t AC0CTRL;  /* Analog Comparator 0 Control */
894    register8_t AC1CTRL;  /* Analog Comparator 1 Control */
895    register8_t AC0MUXCTRL;  /* Analog Comparator 0 MUX Control */
896    register8_t AC1MUXCTRL;  /* Analog Comparator 1 MUX Control */
897    register8_t CTRLA;  /* Control Register A */
898    register8_t CTRLB;  /* Control Register B */
899    register8_t WINCTRL;  /* Window Mode Control */
900    register8_t STATUS;  /* Status */
901} AC_t;
902
903/* Interrupt mode */
904typedef enum AC_INTMODE_enum
905{
906    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
907    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
908    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
909} AC_INTMODE_t;
910
911/* Interrupt level */
912typedef enum AC_INTLVL_enum
913{
914    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
915    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
916    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
917    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
918} AC_INTLVL_t;
919
920/* Hysteresis mode selection */
921typedef enum AC_HYSMODE_enum
922{
923    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
924    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
925    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
926} AC_HYSMODE_t;
927
928/* Positive input multiplexer selection */
929typedef enum AC_MUXPOS_enum
930{
931    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
932    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
933    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
934    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
935    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
936    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
937    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
938    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
939} AC_MUXPOS_t;
940
941/* Negative input multiplexer selection */
942typedef enum AC_MUXNEG_enum
943{
944    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
945    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
946    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
947    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
948    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
949    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
950    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
951    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
952} AC_MUXNEG_t;
953
954/* Windows interrupt mode */
955typedef enum AC_WINTMODE_enum
956{
957    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
958    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
959    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
960    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
961} AC_WINTMODE_t;
962
963/* Window interrupt level */
964typedef enum AC_WINTLVL_enum
965{
966    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
967    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
968    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
969    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
970} AC_WINTLVL_t;
971
972/* Window mode state */
973typedef enum AC_WSTATE_enum
974{
975    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
976    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
977    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
978} AC_WSTATE_t;
979
980
981/*
982--------------------------------------------------------------------------
983ADC - Analog/Digital Converter
984--------------------------------------------------------------------------
985*/
986
987/* ADC Channel */
988typedef struct ADC_CH_struct
989{
990    register8_t CTRL;  /* Control Register */
991    register8_t MUXCTRL;  /* MUX Control */
992    register8_t INTCTRL;  /* Channel Interrupt Control Register */
993    register8_t INTFLAGS;  /* Interrupt Flags */
994    _WORDREGISTER(RES);  /* Channel Result */
995    register8_t SCAN;  /* Input Channel Scan */
996    register8_t reserved_0x07;
997} ADC_CH_t;
998
999
1000/* Analog-to-Digital Converter */
1001typedef struct ADC_struct
1002{
1003    register8_t CTRLA;  /* Control Register A */
1004    register8_t CTRLB;  /* Control Register B */
1005    register8_t REFCTRL;  /* Reference Control */
1006    register8_t EVCTRL;  /* Event Control */
1007    register8_t PRESCALER;  /* Clock Prescaler */
1008    register8_t reserved_0x05;
1009    register8_t INTFLAGS;  /* Interrupt Flags */
1010    register8_t TEMP;  /* Temporary Register */
1011    register8_t reserved_0x08;
1012    register8_t reserved_0x09;
1013    register8_t reserved_0x0A;
1014    register8_t reserved_0x0B;
1015    _WORDREGISTER(CAL);  /* Calibration Value */
1016    register8_t reserved_0x0E;
1017    register8_t reserved_0x0F;
1018    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
1019    register8_t reserved_0x12;
1020    register8_t reserved_0x13;
1021    register8_t reserved_0x14;
1022    register8_t reserved_0x15;
1023    register8_t reserved_0x16;
1024    register8_t reserved_0x17;
1025    _WORDREGISTER(CMP);  /* Compare Value */
1026    register8_t reserved_0x1A;
1027    register8_t reserved_0x1B;
1028    register8_t reserved_0x1C;
1029    register8_t reserved_0x1D;
1030    register8_t reserved_0x1E;
1031    register8_t reserved_0x1F;
1032    ADC_CH_t CH0;  /* ADC Channel 0 */
1033} ADC_t;
1034
1035/* Current Limitation */
1036typedef enum ADC_CURRLIMIT_enum
1037{
1038    ADC_CURRLIMIT_NO_gc = (0x00<<5),  /* No current limit,     300ksps max sampling rate */
1039    ADC_CURRLIMIT_LOW_gc = (0x01<<5),  /* Low current limit,    250ksps max sampling rate */
1040    ADC_CURRLIMIT_MED_gc = (0x02<<5),  /* Medium current limit, 150ksps max sampling rate */
1041    ADC_CURRLIMIT_HIGH_gc = (0x03<<5),  /* High current limit,   50ksps max sampling rate */
1042} ADC_CURRLIMIT_t;
1043
1044/* Positive input multiplexer selection */
1045typedef enum ADC_CH_MUXPOS_enum
1046{
1047    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
1048    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
1049    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
1050    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
1051    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
1052    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
1053    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
1054    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
1055    ADC_CH_MUXPOS_PIN8_gc = (0x08<<3),  /* Input pin 8 */
1056    ADC_CH_MUXPOS_PIN9_gc = (0x09<<3),  /* Input pin 9 */
1057    ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3),  /* Input pin 10 */
1058    ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3),  /* Input pin 11 */
1059    ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3),  /* Input pin 12 */
1060    ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3),  /* Input pin 13 */
1061    ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3),  /* Input pin 14 */
1062    ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3),  /* Input pin 15 */
1063} ADC_CH_MUXPOS_t;
1064
1065/* Internal input multiplexer selections */
1066typedef enum ADC_CH_MUXINT_enum
1067{
1068    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
1069    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
1070    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
1071} ADC_CH_MUXINT_t;
1072
1073/* Negative input multiplexer selection */
1074typedef enum ADC_CH_MUXNEG_enum
1075{
1076    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
1077    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
1078    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
1079    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
1080    ADC_CH_MUXNEG_PIN4_gc = (0x00<<0),  /* Input pin 4 */
1081    ADC_CH_MUXNEG_PIN5_gc = (0x01<<0),  /* Input pin 5 */
1082    ADC_CH_MUXNEG_PIN6_gc = (0x02<<0),  /* Input pin 6 */
1083    ADC_CH_MUXNEG_PIN7_gc = (0x03<<0),  /* Input pin 7 */
1084} ADC_CH_MUXNEG_t;
1085
1086/* Input mode */
1087typedef enum ADC_CH_INPUTMODE_enum
1088{
1089    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
1090    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
1091    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
1092    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
1093} ADC_CH_INPUTMODE_t;
1094
1095/* Gain factor */
1096typedef enum ADC_CH_GAIN_enum
1097{
1098    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
1099    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
1100    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
1101    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
1102    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
1103    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
1104    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
1105    ADC_CH_GAIN_DIV2_gc = (0x07<<2),  /* x/2 gain */
1106} ADC_CH_GAIN_t;
1107
1108/* Conversion result resolution */
1109typedef enum ADC_RESOLUTION_enum
1110{
1111    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
1112    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
1113    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
1114} ADC_RESOLUTION_t;
1115
1116/* Voltage reference selection */
1117typedef enum ADC_REFSEL_enum
1118{
1119    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
1120    ADC_REFSEL_INTVCC_gc = (0x01<<4),  /* Internal VCC / 1.6 */
1121    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
1122    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
1123    ADC_REFSEL_INTVCC2_gc = (0x04<<4),  /* Internal VCC / 2 */
1124} ADC_REFSEL_t;
1125
1126/* Event channel input selection */
1127typedef enum ADC_EVSEL_enum
1128{
1129    ADC_EVSEL_0_gc = (0x00<<3),  /* Event Channel 0 */
1130    ADC_EVSEL_1_gc = (0x01<<3),  /* Event Channel 1 */
1131    ADC_EVSEL_2_gc = (0x02<<3),  /* Event Channel 2 */
1132    ADC_EVSEL_3_gc = (0x03<<3),  /* Event Channel 3 */
1133} ADC_EVSEL_t;
1134
1135/* Event action selection */
1136typedef enum ADC_EVACT_enum
1137{
1138    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
1139    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
1140    ADC_EVACT_SYNCSWEEP_gc = (0x06<<0),  /* The ADC is flushed and restarted for accurate timing */
1141} ADC_EVACT_t;
1142
1143/* Interupt mode */
1144typedef enum ADC_CH_INTMODE_enum
1145{
1146    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
1147    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
1148    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
1149} ADC_CH_INTMODE_t;
1150
1151/* Interrupt level */
1152typedef enum ADC_CH_INTLVL_enum
1153{
1154    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
1155    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
1156    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
1157    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
1158} ADC_CH_INTLVL_t;
1159
1160/* Clock prescaler */
1161typedef enum ADC_PRESCALER_enum
1162{
1163    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
1164    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
1165    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
1166    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
1167    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
1168    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
1169    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
1170    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
1171} ADC_PRESCALER_t;
1172
1173
1174/*
1175--------------------------------------------------------------------------
1176RTC - Real-Time Counter
1177--------------------------------------------------------------------------
1178*/
1179
1180/* Real-Time Counter */
1181typedef struct RTC_struct
1182{
1183    register8_t CTRL;  /* Control Register */
1184    register8_t STATUS;  /* Status Register */
1185    register8_t INTCTRL;  /* Interrupt Control Register */
1186    register8_t INTFLAGS;  /* Interrupt Flags */
1187    register8_t TEMP;  /* Temporary register */
1188    register8_t reserved_0x05;
1189    register8_t reserved_0x06;
1190    register8_t reserved_0x07;
1191    _WORDREGISTER(CNT);  /* Count Register */
1192    _WORDREGISTER(PER);  /* Period Register */
1193    _WORDREGISTER(COMP);  /* Compare Register */
1194} RTC_t;
1195
1196/* Prescaler Factor */
1197typedef enum RTC_PRESCALER_enum
1198{
1199    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
1200    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
1201    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
1202    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
1203    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
1204    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
1205    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
1206    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
1207} RTC_PRESCALER_t;
1208
1209/* Compare Interrupt level */
1210typedef enum RTC_COMPINTLVL_enum
1211{
1212    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1213    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1214    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1215    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
1216} RTC_COMPINTLVL_t;
1217
1218/* Overflow Interrupt level */
1219typedef enum RTC_OVFINTLVL_enum
1220{
1221    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1222    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1223    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1224    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1225} RTC_OVFINTLVL_t;
1226
1227
1228/*
1229--------------------------------------------------------------------------
1230TWI - Two-Wire Interface
1231--------------------------------------------------------------------------
1232*/
1233
1234/*  */
1235typedef struct TWI_MASTER_struct
1236{
1237    register8_t CTRLA;  /* Control Register A */
1238    register8_t CTRLB;  /* Control Register B */
1239    register8_t CTRLC;  /* Control Register C */
1240    register8_t STATUS;  /* Status Register */
1241    register8_t BAUD;  /* Baurd Rate Control Register */
1242    register8_t ADDR;  /* Address Register */
1243    register8_t DATA;  /* Data Register */
1244} TWI_MASTER_t;
1245
1246
1247/*  */
1248typedef struct TWI_SLAVE_struct
1249{
1250    register8_t CTRLA;  /* Control Register A */
1251    register8_t CTRLB;  /* Control Register B */
1252    register8_t STATUS;  /* Status Register */
1253    register8_t ADDR;  /* Address Register */
1254    register8_t DATA;  /* Data Register */
1255    register8_t ADDRMASK;  /* Address Mask Register */
1256} TWI_SLAVE_t;
1257
1258
1259/* Two-Wire Interface */
1260typedef struct TWI_struct
1261{
1262    register8_t CTRL;  /* TWI Common Control Register */
1263    TWI_MASTER_t MASTER;  /* TWI master module */
1264    TWI_SLAVE_t SLAVE;  /* TWI slave module */
1265} TWI_t;
1266
1267/* Master Interrupt Level */
1268typedef enum TWI_MASTER_INTLVL_enum
1269{
1270    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1271    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1272    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1273    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1274} TWI_MASTER_INTLVL_t;
1275
1276/* Inactive Timeout */
1277typedef enum TWI_MASTER_TIMEOUT_enum
1278{
1279    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
1280    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
1281    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
1282    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
1283} TWI_MASTER_TIMEOUT_t;
1284
1285/* Master Command */
1286typedef enum TWI_MASTER_CMD_enum
1287{
1288    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1289    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
1290    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
1291    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
1292} TWI_MASTER_CMD_t;
1293
1294/* Master Bus State */
1295typedef enum TWI_MASTER_BUSSTATE_enum
1296{
1297    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
1298    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
1299    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
1300    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
1301} TWI_MASTER_BUSSTATE_t;
1302
1303/* Slave Interrupt Level */
1304typedef enum TWI_SLAVE_INTLVL_enum
1305{
1306    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1307    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1308    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1309    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1310} TWI_SLAVE_INTLVL_t;
1311
1312/* Slave Command */
1313typedef enum TWI_SLAVE_CMD_enum
1314{
1315    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1316    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
1317    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
1318} TWI_SLAVE_CMD_t;
1319
1320/* SDA hold time */
1321typedef enum SDA_HOLD_TIME_enum
1322{
1323    SDA_HOLD_TIME_OFF_gc = (0x00<<1),  /* SDA hold time off */
1324    SDA_HOLD_TIME_50NS_gc = (0x01<<1),  /* Typical 50ns hold time */
1325    SDA_HOLD_TIME_300NS_gc = (0x02<<1),  /* Typical 300ns hold time */
1326    SDA_HOLD_TIME_400NS_gc = (0x03<<1),  /* Typical 400ns hold time */
1327} SDA_HOLD_TIME_t;
1328
1329
1330/*
1331--------------------------------------------------------------------------
1332PORT - Port Configuration
1333--------------------------------------------------------------------------
1334*/
1335
1336/* I/O port Configuration */
1337typedef struct PORTCFG_struct
1338{
1339    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
1340    register8_t reserved_0x01;
1341    register8_t VPCTRLA;  /* Virtual Port Control Register A */
1342    register8_t VPCTRLB;  /* Virtual Port Control Register B */
1343    register8_t CLKEVOUT;  /* Clock and Event Out Register */
1344} PORTCFG_t;
1345
1346
1347/* Virtual Port */
1348typedef struct VPORT_struct
1349{
1350    register8_t DIR;  /* I/O Port Data Direction */
1351    register8_t OUT;  /* I/O Port Output */
1352    register8_t IN;  /* I/O Port Input */
1353    register8_t INTFLAGS;  /* Interrupt Flag Register */
1354} VPORT_t;
1355
1356
1357/* I/O Ports */
1358typedef struct PORT_struct
1359{
1360    register8_t DIR;  /* I/O Port Data Direction */
1361    register8_t DIRSET;  /* I/O Port Data Direction Set */
1362    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
1363    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
1364    register8_t OUT;  /* I/O Port Output */
1365    register8_t OUTSET;  /* I/O Port Output Set */
1366    register8_t OUTCLR;  /* I/O Port Output Clear */
1367    register8_t OUTTGL;  /* I/O Port Output Toggle */
1368    register8_t IN;  /* I/O port Input */
1369    register8_t INTCTRL;  /* Interrupt Control Register */
1370    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
1371    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
1372    register8_t INTFLAGS;  /* Interrupt Flag Register */
1373    register8_t reserved_0x0D;
1374    register8_t REMAP;  /* Pin Remap Register (available for PORTC to PORTF only) */
1375    register8_t reserved_0x0F;
1376    register8_t PIN0CTRL;  /* Pin 0 Control Register */
1377    register8_t PIN1CTRL;  /* Pin 1 Control Register */
1378    register8_t PIN2CTRL;  /* Pin 2 Control Register */
1379    register8_t PIN3CTRL;  /* Pin 3 Control Register */
1380    register8_t PIN4CTRL;  /* Pin 4 Control Register */
1381    register8_t PIN5CTRL;  /* Pin 5 Control Register */
1382    register8_t PIN6CTRL;  /* Pin 6 Control Register */
1383    register8_t PIN7CTRL;  /* Pin 7 Control Register */
1384} PORT_t;
1385
1386/* Virtual Port 0 Mapping */
1387typedef enum PORTCFG_VP0MAP_enum
1388{
1389    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1390    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1391    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1392    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1393    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1394    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1395    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1396    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1397    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1398    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1399    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1400    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1401    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1402    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1403    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1404    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1405} PORTCFG_VP0MAP_t;
1406
1407/* Virtual Port 1 Mapping */
1408typedef enum PORTCFG_VP1MAP_enum
1409{
1410    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1411    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1412    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1413    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1414    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1415    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1416    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1417    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1418    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1419    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1420    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1421    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1422    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1423    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1424    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1425    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1426} PORTCFG_VP1MAP_t;
1427
1428/* Virtual Port 2 Mapping */
1429typedef enum PORTCFG_VP2MAP_enum
1430{
1431    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1432    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1433    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1434    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1435    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1436    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1437    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1438    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1439    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1440    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1441    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1442    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1443    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1444    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1445    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1446    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1447} PORTCFG_VP2MAP_t;
1448
1449/* Virtual Port 3 Mapping */
1450typedef enum PORTCFG_VP3MAP_enum
1451{
1452    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1453    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1454    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1455    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1456    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1457    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1458    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1459    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1460    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1461    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1462    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1463    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1464    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1465    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1466    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1467    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1468} PORTCFG_VP3MAP_t;
1469
1470/* Clock Output Port */
1471typedef enum PORTCFG_CLKOUT_enum
1472{
1473    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
1474    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
1475    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
1476    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
1477} PORTCFG_CLKOUT_t;
1478
1479/* Event Output Port */
1480typedef enum PORTCFG_EVOUT_enum
1481{
1482    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
1483    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
1484    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
1485    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
1486} PORTCFG_EVOUT_t;
1487
1488/* Port Interrupt 0 Level */
1489typedef enum PORT_INT0LVL_enum
1490{
1491    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1492    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
1493    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
1494    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
1495} PORT_INT0LVL_t;
1496
1497/* Port Interrupt 1 Level */
1498typedef enum PORT_INT1LVL_enum
1499{
1500    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1501    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
1502    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
1503    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
1504} PORT_INT1LVL_t;
1505
1506/* Output/Pull Configuration */
1507typedef enum PORT_OPC_enum
1508{
1509    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
1510    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
1511    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
1512    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
1513    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
1514    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
1515    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
1516    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
1517} PORT_OPC_t;
1518
1519/* Input/Sense Configuration */
1520typedef enum PORT_ISC_enum
1521{
1522    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
1523    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
1524    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
1525    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
1526    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
1527} PORT_ISC_t;
1528
1529
1530/*
1531--------------------------------------------------------------------------
1532TC - 16-bit Timer/Counter With PWM
1533--------------------------------------------------------------------------
1534*/
1535
1536/* 16-bit Timer/Counter 0 */
1537typedef struct TC0_struct
1538{
1539    register8_t CTRLA;  /* Control Register A */
1540    register8_t CTRLB;  /* Control Register B */
1541    register8_t CTRLC;  /* Control register C */
1542    register8_t CTRLD;  /* Control Register D */
1543    register8_t CTRLE;  /* Control Register E */
1544    register8_t reserved_0x05;
1545    register8_t INTCTRLA;  /* Interrupt Control Register A */
1546    register8_t INTCTRLB;  /* Interrupt Control Register B */
1547    register8_t CTRLFCLR;  /* Control Register F Clear */
1548    register8_t CTRLFSET;  /* Control Register F Set */
1549    register8_t CTRLGCLR;  /* Control Register G Clear */
1550    register8_t CTRLGSET;  /* Control Register G Set */
1551    register8_t INTFLAGS;  /* Interrupt Flag Register */
1552    register8_t reserved_0x0D;
1553    register8_t reserved_0x0E;
1554    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1555    register8_t reserved_0x10;
1556    register8_t reserved_0x11;
1557    register8_t reserved_0x12;
1558    register8_t reserved_0x13;
1559    register8_t reserved_0x14;
1560    register8_t reserved_0x15;
1561    register8_t reserved_0x16;
1562    register8_t reserved_0x17;
1563    register8_t reserved_0x18;
1564    register8_t reserved_0x19;
1565    register8_t reserved_0x1A;
1566    register8_t reserved_0x1B;
1567    register8_t reserved_0x1C;
1568    register8_t reserved_0x1D;
1569    register8_t reserved_0x1E;
1570    register8_t reserved_0x1F;
1571    _WORDREGISTER(CNT);  /* Count */
1572    register8_t reserved_0x22;
1573    register8_t reserved_0x23;
1574    register8_t reserved_0x24;
1575    register8_t reserved_0x25;
1576    _WORDREGISTER(PER);  /* Period */
1577    _WORDREGISTER(CCA);  /* Compare or Capture A */
1578    _WORDREGISTER(CCB);  /* Compare or Capture B */
1579    _WORDREGISTER(CCC);  /* Compare or Capture C */
1580    _WORDREGISTER(CCD);  /* Compare or Capture D */
1581    register8_t reserved_0x30;
1582    register8_t reserved_0x31;
1583    register8_t reserved_0x32;
1584    register8_t reserved_0x33;
1585    register8_t reserved_0x34;
1586    register8_t reserved_0x35;
1587    _WORDREGISTER(PERBUF);  /* Period Buffer */
1588    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1589    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1590    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
1591    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
1592} TC0_t;
1593
1594
1595/* 16-bit Timer/Counter 1 */
1596typedef struct TC1_struct
1597{
1598    register8_t CTRLA;  /* Control  Register A */
1599    register8_t CTRLB;  /* Control Register B */
1600    register8_t CTRLC;  /* Control register C */
1601    register8_t CTRLD;  /* Control Register D */
1602    register8_t CTRLE;  /* Control Register E */
1603    register8_t reserved_0x05;
1604    register8_t INTCTRLA;  /* Interrupt Control Register A */
1605    register8_t INTCTRLB;  /* Interrupt Control Register B */
1606    register8_t CTRLFCLR;  /* Control Register F Clear */
1607    register8_t CTRLFSET;  /* Control Register F Set */
1608    register8_t CTRLGCLR;  /* Control Register G Clear */
1609    register8_t CTRLGSET;  /* Control Register G Set */
1610    register8_t INTFLAGS;  /* Interrupt Flag Register */
1611    register8_t reserved_0x0D;
1612    register8_t reserved_0x0E;
1613    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1614    register8_t reserved_0x10;
1615    register8_t reserved_0x11;
1616    register8_t reserved_0x12;
1617    register8_t reserved_0x13;
1618    register8_t reserved_0x14;
1619    register8_t reserved_0x15;
1620    register8_t reserved_0x16;
1621    register8_t reserved_0x17;
1622    register8_t reserved_0x18;
1623    register8_t reserved_0x19;
1624    register8_t reserved_0x1A;
1625    register8_t reserved_0x1B;
1626    register8_t reserved_0x1C;
1627    register8_t reserved_0x1D;
1628    register8_t reserved_0x1E;
1629    register8_t reserved_0x1F;
1630    _WORDREGISTER(CNT);  /* Count */
1631    register8_t reserved_0x22;
1632    register8_t reserved_0x23;
1633    register8_t reserved_0x24;
1634    register8_t reserved_0x25;
1635    _WORDREGISTER(PER);  /* Period */
1636    _WORDREGISTER(CCA);  /* Compare or Capture A */
1637    _WORDREGISTER(CCB);  /* Compare or Capture B */
1638    register8_t reserved_0x2C;
1639    register8_t reserved_0x2D;
1640    register8_t reserved_0x2E;
1641    register8_t reserved_0x2F;
1642    register8_t reserved_0x30;
1643    register8_t reserved_0x31;
1644    register8_t reserved_0x32;
1645    register8_t reserved_0x33;
1646    register8_t reserved_0x34;
1647    register8_t reserved_0x35;
1648    _WORDREGISTER(PERBUF);  /* Period Buffer */
1649    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1650    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1651} TC1_t;
1652
1653
1654/* Advanced Waveform Extension */
1655typedef struct AWEX_struct
1656{
1657    register8_t CTRL;  /* Control Register */
1658    register8_t reserved_0x01;
1659    register8_t FDEMASK;  /* Fault Detection Event Mask */
1660    register8_t FDCTRL;  /* Fault Detection Control Register */
1661    register8_t STATUS;  /* Status Register */
1662    register8_t reserved_0x05;
1663    register8_t DTBOTH;  /* Dead Time Both Sides */
1664    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
1665    register8_t DTLS;  /* Dead Time Low Side */
1666    register8_t DTHS;  /* Dead Time High Side */
1667    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
1668    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
1669    register8_t OUTOVEN;  /* Output Override Enable */
1670} AWEX_t;
1671
1672
1673/* High-Resolution Extension */
1674typedef struct HIRES_struct
1675{
1676    register8_t CTRLA;  /* Control Register */
1677} HIRES_t;
1678
1679/* Clock Selection */
1680typedef enum TC_CLKSEL_enum
1681{
1682    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
1683    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
1684    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
1685    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
1686    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
1687    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
1688    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
1689    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
1690    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
1691    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
1692    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
1693    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
1694    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
1695    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
1696    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
1697    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
1698} TC_CLKSEL_t;
1699
1700/* Waveform Generation Mode */
1701typedef enum TC_WGMODE_enum
1702{
1703    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
1704    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
1705    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
1706    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
1707    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
1708    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
1709} TC_WGMODE_t;
1710
1711/* Event Action */
1712typedef enum TC_EVACT_enum
1713{
1714    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
1715    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
1716    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
1717    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
1718    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
1719    TC_EVACT_FRQ_gc = (0x05<<5),  /* Frequency Capture */
1720    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
1721} TC_EVACT_t;
1722
1723/* Event Selection */
1724typedef enum TC_EVSEL_enum
1725{
1726    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
1727    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
1728    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
1729    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
1730    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
1731    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
1732    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
1733    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
1734    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
1735} TC_EVSEL_t;
1736
1737/* Error Interrupt Level */
1738typedef enum TC_ERRINTLVL_enum
1739{
1740    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1741    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1742    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1743    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
1744} TC_ERRINTLVL_t;
1745
1746/* Overflow Interrupt Level */
1747typedef enum TC_OVFINTLVL_enum
1748{
1749    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1750    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1751    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1752    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1753} TC_OVFINTLVL_t;
1754
1755/* Compare or Capture D Interrupt Level */
1756typedef enum TC_CCDINTLVL_enum
1757{
1758    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1759    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
1760    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1761    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
1762} TC_CCDINTLVL_t;
1763
1764/* Compare or Capture C Interrupt Level */
1765typedef enum TC_CCCINTLVL_enum
1766{
1767    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
1768    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
1769    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
1770    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
1771} TC_CCCINTLVL_t;
1772
1773/* Compare or Capture B Interrupt Level */
1774typedef enum TC_CCBINTLVL_enum
1775{
1776    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1777    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1778    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1779    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
1780} TC_CCBINTLVL_t;
1781
1782/* Compare or Capture A Interrupt Level */
1783typedef enum TC_CCAINTLVL_enum
1784{
1785    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1786    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1787    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1788    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
1789} TC_CCAINTLVL_t;
1790
1791/* Timer/Counter Command */
1792typedef enum TC_CMD_enum
1793{
1794    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
1795    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
1796    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
1797    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
1798} TC_CMD_t;
1799
1800/* Fault Detect Action */
1801typedef enum AWEX_FDACT_enum
1802{
1803    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
1804    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
1805    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
1806} AWEX_FDACT_t;
1807
1808/* High Resolution Enable */
1809typedef enum HIRES_HREN_enum
1810{
1811    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
1812    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
1813    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
1814    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
1815} HIRES_HREN_t;
1816
1817
1818/*
1819--------------------------------------------------------------------------
1820USART - Universal Asynchronous Receiver-Transmitter
1821--------------------------------------------------------------------------
1822*/
1823
1824/* Universal Synchronous/Asynchronous Receiver/Transmitter */
1825typedef struct USART_struct
1826{
1827    register8_t DATA;  /* Data Register */
1828    register8_t STATUS;  /* Status Register */
1829    register8_t reserved_0x02;
1830    register8_t CTRLA;  /* Control Register A */
1831    register8_t CTRLB;  /* Control Register B */
1832    register8_t CTRLC;  /* Control Register C */
1833    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
1834    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
1835} USART_t;
1836
1837/* Receive Complete Interrupt level */
1838typedef enum USART_RXCINTLVL_enum
1839{
1840    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
1841    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
1842    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
1843    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
1844} USART_RXCINTLVL_t;
1845
1846/* Transmit Complete Interrupt level */
1847typedef enum USART_TXCINTLVL_enum
1848{
1849    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1850    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1851    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1852    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
1853} USART_TXCINTLVL_t;
1854
1855/* Data Register Empty Interrupt level */
1856typedef enum USART_DREINTLVL_enum
1857{
1858    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1859    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1860    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1861    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
1862} USART_DREINTLVL_t;
1863
1864/* Character Size */
1865typedef enum USART_CHSIZE_enum
1866{
1867    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
1868    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
1869    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
1870    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
1871    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
1872} USART_CHSIZE_t;
1873
1874/* Communication Mode */
1875typedef enum USART_CMODE_enum
1876{
1877    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
1878    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
1879    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
1880    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
1881} USART_CMODE_t;
1882
1883/* Parity Mode */
1884typedef enum USART_PMODE_enum
1885{
1886    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
1887    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
1888    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
1889} USART_PMODE_t;
1890
1891
1892/*
1893--------------------------------------------------------------------------
1894SPI - Serial Peripheral Interface
1895--------------------------------------------------------------------------
1896*/
1897
1898/* Serial Peripheral Interface */
1899typedef struct SPI_struct
1900{
1901    register8_t CTRL;  /* Control Register */
1902    register8_t INTCTRL;  /* Interrupt Control Register */
1903    register8_t STATUS;  /* Status Register */
1904    register8_t DATA;  /* Data Register */
1905} SPI_t;
1906
1907/* SPI Mode */
1908typedef enum SPI_MODE_enum
1909{
1910    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
1911    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
1912    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
1913    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
1914} SPI_MODE_t;
1915
1916/* Prescaler setting */
1917typedef enum SPI_PRESCALER_enum
1918{
1919    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
1920    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
1921    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
1922    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
1923} SPI_PRESCALER_t;
1924
1925/* Interrupt level */
1926typedef enum SPI_INTLVL_enum
1927{
1928    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1929    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
1930    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1931    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
1932} SPI_INTLVL_t;
1933
1934
1935/*
1936--------------------------------------------------------------------------
1937IRCOM - IR Communication Module
1938--------------------------------------------------------------------------
1939*/
1940
1941/* IR Communication Module */
1942typedef struct IRCOM_struct
1943{
1944    register8_t CTRL;  /* Control Register */
1945    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
1946    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
1947} IRCOM_t;
1948
1949/* Event channel selection */
1950typedef enum IRDA_EVSEL_enum
1951{
1952    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
1953    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
1954    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
1955    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
1956    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
1957    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
1958    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
1959    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
1960    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
1961} IRDA_EVSEL_t;
1962
1963/*
1964==========================================================================
1965IO Module Instances. Mapped to memory.
1966==========================================================================
1967*/
1968
1969#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port */
1970#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port */
1971#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port */
1972#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port */
1973#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
1974#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
1975#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
1976#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator */
1977#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL */
1978#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL */
1979#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
1980#define RST    (*(RST_t *) 0x0078)  /* Reset */
1981#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
1982#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
1983#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Multi-level Interrupt Controller */
1984#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* I/O port Configuration */
1985#define CRC    (*(CRC_t *) 0x00D0)  /* Cyclic Redundancy Checker */
1986#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
1987#define NVM    (*(NVM_t *) 0x01C0)  /* Non-volatile Memory Controller */
1988#define ADCA    (*(ADC_t *) 0x0200)  /* Analog-to-Digital Converter */
1989#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator */
1990#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
1991#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface */
1992#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface */
1993#define PORTA    (*(PORT_t *) 0x0600)  /* I/O Ports */
1994#define PORTB    (*(PORT_t *) 0x0620)  /* I/O Ports */
1995#define PORTC    (*(PORT_t *) 0x0640)  /* I/O Ports */
1996#define PORTD    (*(PORT_t *) 0x0660)  /* I/O Ports */
1997#define PORTE    (*(PORT_t *) 0x0680)  /* I/O Ports */
1998#define PORTF    (*(PORT_t *) 0x06A0)  /* I/O Ports */
1999#define PORTR    (*(PORT_t *) 0x07E0)  /* I/O Ports */
2000#define TCC0    (*(TC0_t *) 0x0800)  /* 16-bit Timer/Counter 0 */
2001#define TCC1    (*(TC1_t *) 0x0840)  /* 16-bit Timer/Counter 1 */
2002#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension */
2003#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension */
2004#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
2005#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface */
2006#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
2007#define TCD0    (*(TC0_t *) 0x0900)  /* 16-bit Timer/Counter 0 */
2008#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
2009#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface */
2010#define TCE0    (*(TC0_t *) 0x0A00)  /* 16-bit Timer/Counter 0 */
2011#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension */
2012#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Synchronous/Asynchronous Receiver/Transmitter */
2013#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface */
2014#define TCF0    (*(TC0_t *) 0x0B00)  /* 16-bit Timer/Counter 0 */
2015
2016
2017#endif /* !defined (__ASSEMBLER__) */
2018
2019
2020/* ========== Flattened fully qualified IO register names ========== */
2021
2022/* GPIO - General Purpose IO Registers */
2023#define GPIO_GPIOR0  _SFR_MEM8(0x0000)
2024#define GPIO_GPIOR1  _SFR_MEM8(0x0001)
2025#define GPIO_GPIOR2  _SFR_MEM8(0x0002)
2026#define GPIO_GPIOR3  _SFR_MEM8(0x0003)
2027
2028/* Deprecated */
2029#define GPIO_GPIO0  _SFR_MEM8(0x0000)
2030#define GPIO_GPIO1  _SFR_MEM8(0x0001)
2031#define GPIO_GPIO2  _SFR_MEM8(0x0002)
2032#define GPIO_GPIO3  _SFR_MEM8(0x0003)
2033
2034/* NVM_FUSES - Fuses */
2035#define FUSE_FUSEBYTE1  _SFR_MEM8(0x0001)
2036#define FUSE_FUSEBYTE2  _SFR_MEM8(0x0002)
2037#define FUSE_FUSEBYTE4  _SFR_MEM8(0x0004)
2038#define FUSE_FUSEBYTE5  _SFR_MEM8(0x0005)
2039
2040/* NVM_LOCKBITS - Lock Bits */
2041#define LOCKBIT_LOCKBITS  _SFR_MEM8(0x0000)
2042
2043/* NVM_PROD_SIGNATURES - Production Signatures */
2044#define PRODSIGNATURES_RCOSC2M  _SFR_MEM8(0x0000)
2045#define PRODSIGNATURES_RCOSC32K  _SFR_MEM8(0x0002)
2046#define PRODSIGNATURES_RCOSC32M  _SFR_MEM8(0x0003)
2047#define PRODSIGNATURES_LOTNUM0  _SFR_MEM8(0x0008)
2048#define PRODSIGNATURES_LOTNUM1  _SFR_MEM8(0x0009)
2049#define PRODSIGNATURES_LOTNUM2  _SFR_MEM8(0x000A)
2050#define PRODSIGNATURES_LOTNUM3  _SFR_MEM8(0x000B)
2051#define PRODSIGNATURES_LOTNUM4  _SFR_MEM8(0x000C)
2052#define PRODSIGNATURES_LOTNUM5  _SFR_MEM8(0x000D)
2053#define PRODSIGNATURES_WAFNUM  _SFR_MEM8(0x0010)
2054#define PRODSIGNATURES_COORDX0  _SFR_MEM8(0x0012)
2055#define PRODSIGNATURES_COORDX1  _SFR_MEM8(0x0013)
2056#define PRODSIGNATURES_COORDY0  _SFR_MEM8(0x0014)
2057#define PRODSIGNATURES_COORDY1  _SFR_MEM8(0x0015)
2058#define PRODSIGNATURES_ADCACAL0  _SFR_MEM8(0x0020)
2059#define PRODSIGNATURES_ADCACAL1  _SFR_MEM8(0x0021)
2060#define PRODSIGNATURES_ADCBCAL0  _SFR_MEM8(0x0024)
2061#define PRODSIGNATURES_ADCBCAL1  _SFR_MEM8(0x0025)
2062#define PRODSIGNATURES_TEMPSENSE0  _SFR_MEM8(0x002E)
2063#define PRODSIGNATURES_TEMPSENSE1  _SFR_MEM8(0x002F)
2064
2065/* VPORT - Virtual Port */
2066#define VPORT0_DIR  _SFR_MEM8(0x0010)
2067#define VPORT0_OUT  _SFR_MEM8(0x0011)
2068#define VPORT0_IN  _SFR_MEM8(0x0012)
2069#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
2070
2071/* VPORT - Virtual Port */
2072#define VPORT1_DIR  _SFR_MEM8(0x0014)
2073#define VPORT1_OUT  _SFR_MEM8(0x0015)
2074#define VPORT1_IN  _SFR_MEM8(0x0016)
2075#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
2076
2077/* VPORT - Virtual Port */
2078#define VPORT2_DIR  _SFR_MEM8(0x0018)
2079#define VPORT2_OUT  _SFR_MEM8(0x0019)
2080#define VPORT2_IN  _SFR_MEM8(0x001A)
2081#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
2082
2083/* VPORT - Virtual Port */
2084#define VPORT3_DIR  _SFR_MEM8(0x001C)
2085#define VPORT3_OUT  _SFR_MEM8(0x001D)
2086#define VPORT3_IN  _SFR_MEM8(0x001E)
2087#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
2088
2089/* OCD - On-Chip Debug System */
2090#define OCD_OCDR0  _SFR_MEM8(0x002E)
2091#define OCD_OCDR1  _SFR_MEM8(0x002F)
2092
2093/* CPU - CPU registers */
2094#define CPU_CCP  _SFR_MEM8(0x0034)
2095#define CPU_RAMPD  _SFR_MEM8(0x0038)
2096#define CPU_RAMPX  _SFR_MEM8(0x0039)
2097#define CPU_RAMPY  _SFR_MEM8(0x003A)
2098#define CPU_RAMPZ  _SFR_MEM8(0x003B)
2099#define CPU_EIND  _SFR_MEM8(0x003C)
2100#define CPU_SPL  _SFR_MEM8(0x003D)
2101#define CPU_SPH  _SFR_MEM8(0x003E)
2102#define CPU_SREG  _SFR_MEM8(0x003F)
2103
2104/* CLK - Clock System */
2105#define CLK_CTRL  _SFR_MEM8(0x0040)
2106#define CLK_PSCTRL  _SFR_MEM8(0x0041)
2107#define CLK_LOCK  _SFR_MEM8(0x0042)
2108#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
2109
2110/* SLEEP - Sleep Controller */
2111#define SLEEP_CTRL  _SFR_MEM8(0x0048)
2112
2113/* OSC - Oscillator */
2114#define OSC_CTRL  _SFR_MEM8(0x0050)
2115#define OSC_STATUS  _SFR_MEM8(0x0051)
2116#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
2117#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
2118#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
2119#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
2120#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
2121
2122/* DFLL - DFLL */
2123#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
2124#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
2125#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
2126#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
2127#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
2128#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
2129
2130/* DFLL - DFLL */
2131#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
2132#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
2133#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
2134#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
2135#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
2136#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
2137
2138/* PR - Power Reduction */
2139#define PR_PRGEN  _SFR_MEM8(0x0070)
2140#define PR_PRPA  _SFR_MEM8(0x0071)
2141#define PR_PRPC  _SFR_MEM8(0x0073)
2142#define PR_PRPD  _SFR_MEM8(0x0074)
2143#define PR_PRPE  _SFR_MEM8(0x0075)
2144#define PR_PRPF  _SFR_MEM8(0x0076)
2145
2146/* RST - Reset */
2147#define RST_STATUS  _SFR_MEM8(0x0078)
2148#define RST_CTRL  _SFR_MEM8(0x0079)
2149
2150/* WDT - Watch-Dog Timer */
2151#define WDT_CTRL  _SFR_MEM8(0x0080)
2152#define WDT_WINCTRL  _SFR_MEM8(0x0081)
2153#define WDT_STATUS  _SFR_MEM8(0x0082)
2154
2155/* MCU - MCU Control */
2156#define MCU_DEVID0  _SFR_MEM8(0x0090)
2157#define MCU_DEVID1  _SFR_MEM8(0x0091)
2158#define MCU_DEVID2  _SFR_MEM8(0x0092)
2159#define MCU_REVID  _SFR_MEM8(0x0093)
2160#define MCU_JTAGUID  _SFR_MEM8(0x0094)
2161#define MCU_MCUCR  _SFR_MEM8(0x0096)
2162#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
2163#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
2164
2165/* PMIC - Programmable Multi-level Interrupt Controller */
2166#define PMIC_STATUS  _SFR_MEM8(0x00A0)
2167#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
2168#define PMIC_CTRL  _SFR_MEM8(0x00A2)
2169
2170/* PORTCFG - I/O port Configuration */
2171#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
2172#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
2173#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
2174#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
2175
2176/* CRC - Cyclic Redundancy Checker */
2177#define CRC_CTRL  _SFR_MEM8(0x00D0)
2178#define CRC_STATUS  _SFR_MEM8(0x00D1)
2179#define CRC_DATAIN  _SFR_MEM8(0x00D3)
2180#define CRC_CHECKSUM0  _SFR_MEM8(0x00D4)
2181#define CRC_CHECKSUM1  _SFR_MEM8(0x00D5)
2182#define CRC_CHECKSUM2  _SFR_MEM8(0x00D6)
2183#define CRC_CHECKSUM3  _SFR_MEM8(0x00D7)
2184
2185/* EVSYS - Event System */
2186#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
2187#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
2188#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
2189#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
2190#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
2191#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
2192#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
2193#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
2194#define EVSYS_STROBE  _SFR_MEM8(0x0190)
2195#define EVSYS_DATA  _SFR_MEM8(0x0191)
2196
2197/* NVM - Non-volatile Memory Controller */
2198#define NVM_ADDR0  _SFR_MEM8(0x01C0)
2199#define NVM_ADDR1  _SFR_MEM8(0x01C1)
2200#define NVM_ADDR2  _SFR_MEM8(0x01C2)
2201#define NVM_DATA0  _SFR_MEM8(0x01C4)
2202#define NVM_DATA1  _SFR_MEM8(0x01C5)
2203#define NVM_DATA2  _SFR_MEM8(0x01C6)
2204#define NVM_CMD  _SFR_MEM8(0x01CA)
2205#define NVM_CTRLA  _SFR_MEM8(0x01CB)
2206#define NVM_CTRLB  _SFR_MEM8(0x01CC)
2207#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
2208#define NVM_STATUS  _SFR_MEM8(0x01CF)
2209#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
2210
2211/* ADC - Analog-to-Digital Converter */
2212#define ADCA_CTRLA  _SFR_MEM8(0x0200)
2213#define ADCA_CTRLB  _SFR_MEM8(0x0201)
2214#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
2215#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
2216#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
2217#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
2218#define ADCA_TEMP  _SFR_MEM8(0x0207)
2219#define ADCA_CAL  _SFR_MEM16(0x020C)
2220#define ADCA_CH0RES  _SFR_MEM16(0x0210)
2221#define ADCA_CMP  _SFR_MEM16(0x0218)
2222#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
2223#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
2224#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
2225#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
2226#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
2227#define ADCA_CH0_SCAN  _SFR_MEM8(0x0226)
2228
2229/* AC - Analog Comparator */
2230#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
2231#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
2232#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
2233#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
2234#define ACA_CTRLA  _SFR_MEM8(0x0384)
2235#define ACA_CTRLB  _SFR_MEM8(0x0385)
2236#define ACA_WINCTRL  _SFR_MEM8(0x0386)
2237#define ACA_STATUS  _SFR_MEM8(0x0387)
2238
2239/* RTC - Real-Time Counter */
2240#define RTC_CTRL  _SFR_MEM8(0x0400)
2241#define RTC_STATUS  _SFR_MEM8(0x0401)
2242#define RTC_INTCTRL  _SFR_MEM8(0x0402)
2243#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
2244#define RTC_TEMP  _SFR_MEM8(0x0404)
2245#define RTC_CNT  _SFR_MEM16(0x0408)
2246#define RTC_PER  _SFR_MEM16(0x040A)
2247#define RTC_COMP  _SFR_MEM16(0x040C)
2248
2249/* TWI - Two-Wire Interface */
2250#define TWIC_CTRL  _SFR_MEM8(0x0480)
2251#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
2252#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
2253#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
2254#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
2255#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
2256#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
2257#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
2258#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
2259#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
2260#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
2261#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
2262#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
2263#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
2264
2265/* TWI - Two-Wire Interface */
2266#define TWIE_CTRL  _SFR_MEM8(0x04A0)
2267#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
2268#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
2269#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
2270#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
2271#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
2272#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
2273#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
2274#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
2275#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
2276#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
2277#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
2278#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
2279#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
2280
2281/* PORT - I/O Ports */
2282#define PORTA_DIR  _SFR_MEM8(0x0600)
2283#define PORTA_DIRSET  _SFR_MEM8(0x0601)
2284#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
2285#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
2286#define PORTA_OUT  _SFR_MEM8(0x0604)
2287#define PORTA_OUTSET  _SFR_MEM8(0x0605)
2288#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
2289#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
2290#define PORTA_IN  _SFR_MEM8(0x0608)
2291#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
2292#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
2293#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
2294#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
2295#define PORTA_REMAP  _SFR_MEM8(0x060E)
2296#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
2297#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
2298#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
2299#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
2300#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
2301#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
2302#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
2303#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
2304
2305/* PORT - I/O Ports */
2306#define PORTB_DIR  _SFR_MEM8(0x0620)
2307#define PORTB_DIRSET  _SFR_MEM8(0x0621)
2308#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
2309#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
2310#define PORTB_OUT  _SFR_MEM8(0x0624)
2311#define PORTB_OUTSET  _SFR_MEM8(0x0625)
2312#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
2313#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
2314#define PORTB_IN  _SFR_MEM8(0x0628)
2315#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
2316#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
2317#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
2318#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
2319#define PORTB_REMAP  _SFR_MEM8(0x062E)
2320#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
2321#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
2322#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
2323#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
2324#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
2325#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
2326#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
2327#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
2328
2329/* PORT - I/O Ports */
2330#define PORTC_DIR  _SFR_MEM8(0x0640)
2331#define PORTC_DIRSET  _SFR_MEM8(0x0641)
2332#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
2333#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
2334#define PORTC_OUT  _SFR_MEM8(0x0644)
2335#define PORTC_OUTSET  _SFR_MEM8(0x0645)
2336#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
2337#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
2338#define PORTC_IN  _SFR_MEM8(0x0648)
2339#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
2340#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
2341#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
2342#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
2343#define PORTC_REMAP  _SFR_MEM8(0x064E)
2344#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
2345#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
2346#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
2347#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
2348#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
2349#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
2350#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
2351#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
2352
2353/* PORT - I/O Ports */
2354#define PORTD_DIR  _SFR_MEM8(0x0660)
2355#define PORTD_DIRSET  _SFR_MEM8(0x0661)
2356#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
2357#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
2358#define PORTD_OUT  _SFR_MEM8(0x0664)
2359#define PORTD_OUTSET  _SFR_MEM8(0x0665)
2360#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
2361#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
2362#define PORTD_IN  _SFR_MEM8(0x0668)
2363#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
2364#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
2365#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
2366#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
2367#define PORTD_REMAP  _SFR_MEM8(0x066E)
2368#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
2369#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
2370#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
2371#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
2372#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
2373#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
2374#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
2375#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
2376
2377/* PORT - I/O Ports */
2378#define PORTE_DIR  _SFR_MEM8(0x0680)
2379#define PORTE_DIRSET  _SFR_MEM8(0x0681)
2380#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
2381#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
2382#define PORTE_OUT  _SFR_MEM8(0x0684)
2383#define PORTE_OUTSET  _SFR_MEM8(0x0685)
2384#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
2385#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
2386#define PORTE_IN  _SFR_MEM8(0x0688)
2387#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
2388#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
2389#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
2390#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
2391#define PORTE_REMAP  _SFR_MEM8(0x068E)
2392#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
2393#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
2394#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
2395#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
2396#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
2397#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
2398#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
2399#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
2400
2401/* PORT - I/O Ports */
2402#define PORTF_DIR  _SFR_MEM8(0x06A0)
2403#define PORTF_DIRSET  _SFR_MEM8(0x06A1)
2404#define PORTF_DIRCLR  _SFR_MEM8(0x06A2)
2405#define PORTF_DIRTGL  _SFR_MEM8(0x06A3)
2406#define PORTF_OUT  _SFR_MEM8(0x06A4)
2407#define PORTF_OUTSET  _SFR_MEM8(0x06A5)
2408#define PORTF_OUTCLR  _SFR_MEM8(0x06A6)
2409#define PORTF_OUTTGL  _SFR_MEM8(0x06A7)
2410#define PORTF_IN  _SFR_MEM8(0x06A8)
2411#define PORTF_INTCTRL  _SFR_MEM8(0x06A9)
2412#define PORTF_INT0MASK  _SFR_MEM8(0x06AA)
2413#define PORTF_INT1MASK  _SFR_MEM8(0x06AB)
2414#define PORTF_INTFLAGS  _SFR_MEM8(0x06AC)
2415#define PORTF_REMAP  _SFR_MEM8(0x06AE)
2416#define PORTF_PIN0CTRL  _SFR_MEM8(0x06B0)
2417#define PORTF_PIN1CTRL  _SFR_MEM8(0x06B1)
2418#define PORTF_PIN2CTRL  _SFR_MEM8(0x06B2)
2419#define PORTF_PIN3CTRL  _SFR_MEM8(0x06B3)
2420#define PORTF_PIN4CTRL  _SFR_MEM8(0x06B4)
2421#define PORTF_PIN5CTRL  _SFR_MEM8(0x06B5)
2422#define PORTF_PIN6CTRL  _SFR_MEM8(0x06B6)
2423#define PORTF_PIN7CTRL  _SFR_MEM8(0x06B7)
2424
2425/* PORT - I/O Ports */
2426#define PORTR_DIR  _SFR_MEM8(0x07E0)
2427#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
2428#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
2429#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
2430#define PORTR_OUT  _SFR_MEM8(0x07E4)
2431#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
2432#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
2433#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
2434#define PORTR_IN  _SFR_MEM8(0x07E8)
2435#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
2436#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
2437#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
2438#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
2439#define PORTR_REMAP  _SFR_MEM8(0x07EE)
2440#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
2441#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
2442#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
2443#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
2444#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
2445#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
2446#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
2447#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
2448
2449/* TC0 - 16-bit Timer/Counter 0 */
2450#define TCC0_CTRLA  _SFR_MEM8(0x0800)
2451#define TCC0_CTRLB  _SFR_MEM8(0x0801)
2452#define TCC0_CTRLC  _SFR_MEM8(0x0802)
2453#define TCC0_CTRLD  _SFR_MEM8(0x0803)
2454#define TCC0_CTRLE  _SFR_MEM8(0x0804)
2455#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
2456#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
2457#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
2458#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
2459#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
2460#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
2461#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
2462#define TCC0_TEMP  _SFR_MEM8(0x080F)
2463#define TCC0_CNT  _SFR_MEM16(0x0820)
2464#define TCC0_PER  _SFR_MEM16(0x0826)
2465#define TCC0_CCA  _SFR_MEM16(0x0828)
2466#define TCC0_CCB  _SFR_MEM16(0x082A)
2467#define TCC0_CCC  _SFR_MEM16(0x082C)
2468#define TCC0_CCD  _SFR_MEM16(0x082E)
2469#define TCC0_PERBUF  _SFR_MEM16(0x0836)
2470#define TCC0_CCABUF  _SFR_MEM16(0x0838)
2471#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
2472#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
2473#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
2474
2475/* TC1 - 16-bit Timer/Counter 1 */
2476#define TCC1_CTRLA  _SFR_MEM8(0x0840)
2477#define TCC1_CTRLB  _SFR_MEM8(0x0841)
2478#define TCC1_CTRLC  _SFR_MEM8(0x0842)
2479#define TCC1_CTRLD  _SFR_MEM8(0x0843)
2480#define TCC1_CTRLE  _SFR_MEM8(0x0844)
2481#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
2482#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
2483#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
2484#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
2485#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
2486#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
2487#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
2488#define TCC1_TEMP  _SFR_MEM8(0x084F)
2489#define TCC1_CNT  _SFR_MEM16(0x0860)
2490#define TCC1_PER  _SFR_MEM16(0x0866)
2491#define TCC1_CCA  _SFR_MEM16(0x0868)
2492#define TCC1_CCB  _SFR_MEM16(0x086A)
2493#define TCC1_PERBUF  _SFR_MEM16(0x0876)
2494#define TCC1_CCABUF  _SFR_MEM16(0x0878)
2495#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
2496
2497/* AWEX - Advanced Waveform Extension */
2498#define AWEXC_CTRL  _SFR_MEM8(0x0880)
2499#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
2500#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
2501#define AWEXC_STATUS  _SFR_MEM8(0x0884)
2502#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
2503#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
2504#define AWEXC_DTLS  _SFR_MEM8(0x0888)
2505#define AWEXC_DTHS  _SFR_MEM8(0x0889)
2506#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
2507#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
2508#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
2509
2510/* HIRES - High-Resolution Extension */
2511#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
2512
2513/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
2514#define USARTC0_DATA  _SFR_MEM8(0x08A0)
2515#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
2516#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
2517#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
2518#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
2519#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
2520#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
2521
2522/* SPI - Serial Peripheral Interface */
2523#define SPIC_CTRL  _SFR_MEM8(0x08C0)
2524#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
2525#define SPIC_STATUS  _SFR_MEM8(0x08C2)
2526#define SPIC_DATA  _SFR_MEM8(0x08C3)
2527
2528/* IRCOM - IR Communication Module */
2529#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
2530#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
2531#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
2532
2533/* TC0 - 16-bit Timer/Counter 0 */
2534#define TCD0_CTRLA  _SFR_MEM8(0x0900)
2535#define TCD0_CTRLB  _SFR_MEM8(0x0901)
2536#define TCD0_CTRLC  _SFR_MEM8(0x0902)
2537#define TCD0_CTRLD  _SFR_MEM8(0x0903)
2538#define TCD0_CTRLE  _SFR_MEM8(0x0904)
2539#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
2540#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
2541#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
2542#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
2543#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
2544#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
2545#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
2546#define TCD0_TEMP  _SFR_MEM8(0x090F)
2547#define TCD0_CNT  _SFR_MEM16(0x0920)
2548#define TCD0_PER  _SFR_MEM16(0x0926)
2549#define TCD0_CCA  _SFR_MEM16(0x0928)
2550#define TCD0_CCB  _SFR_MEM16(0x092A)
2551#define TCD0_CCC  _SFR_MEM16(0x092C)
2552#define TCD0_CCD  _SFR_MEM16(0x092E)
2553#define TCD0_PERBUF  _SFR_MEM16(0x0936)
2554#define TCD0_CCABUF  _SFR_MEM16(0x0938)
2555#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
2556#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
2557#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
2558
2559/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
2560#define USARTD0_DATA  _SFR_MEM8(0x09A0)
2561#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
2562#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
2563#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
2564#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
2565#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
2566#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
2567
2568/* SPI - Serial Peripheral Interface */
2569#define SPID_CTRL  _SFR_MEM8(0x09C0)
2570#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
2571#define SPID_STATUS  _SFR_MEM8(0x09C2)
2572#define SPID_DATA  _SFR_MEM8(0x09C3)
2573
2574/* TC0 - 16-bit Timer/Counter 0 */
2575#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
2576#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
2577#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
2578#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
2579#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
2580#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
2581#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
2582#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
2583#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
2584#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
2585#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
2586#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
2587#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
2588#define TCE0_CNT  _SFR_MEM16(0x0A20)
2589#define TCE0_PER  _SFR_MEM16(0x0A26)
2590#define TCE0_CCA  _SFR_MEM16(0x0A28)
2591#define TCE0_CCB  _SFR_MEM16(0x0A2A)
2592#define TCE0_CCC  _SFR_MEM16(0x0A2C)
2593#define TCE0_CCD  _SFR_MEM16(0x0A2E)
2594#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
2595#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
2596#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
2597#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
2598#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
2599
2600/* AWEX - Advanced Waveform Extension */
2601#define AWEXE_CTRL  _SFR_MEM8(0x0A80)
2602#define AWEXE_FDEMASK  _SFR_MEM8(0x0A82)
2603#define AWEXE_FDCTRL  _SFR_MEM8(0x0A83)
2604#define AWEXE_STATUS  _SFR_MEM8(0x0A84)
2605#define AWEXE_DTBOTH  _SFR_MEM8(0x0A86)
2606#define AWEXE_DTBOTHBUF  _SFR_MEM8(0x0A87)
2607#define AWEXE_DTLS  _SFR_MEM8(0x0A88)
2608#define AWEXE_DTHS  _SFR_MEM8(0x0A89)
2609#define AWEXE_DTLSBUF  _SFR_MEM8(0x0A8A)
2610#define AWEXE_DTHSBUF  _SFR_MEM8(0x0A8B)
2611#define AWEXE_OUTOVEN  _SFR_MEM8(0x0A8C)
2612
2613/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
2614#define USARTE0_DATA  _SFR_MEM8(0x0AA0)
2615#define USARTE0_STATUS  _SFR_MEM8(0x0AA1)
2616#define USARTE0_CTRLA  _SFR_MEM8(0x0AA3)
2617#define USARTE0_CTRLB  _SFR_MEM8(0x0AA4)
2618#define USARTE0_CTRLC  _SFR_MEM8(0x0AA5)
2619#define USARTE0_BAUDCTRLA  _SFR_MEM8(0x0AA6)
2620#define USARTE0_BAUDCTRLB  _SFR_MEM8(0x0AA7)
2621
2622/* SPI - Serial Peripheral Interface */
2623#define SPIE_CTRL  _SFR_MEM8(0x0AC0)
2624#define SPIE_INTCTRL  _SFR_MEM8(0x0AC1)
2625#define SPIE_STATUS  _SFR_MEM8(0x0AC2)
2626#define SPIE_DATA  _SFR_MEM8(0x0AC3)
2627
2628/* TC0 - 16-bit Timer/Counter 0 */
2629#define TCF0_CTRLA  _SFR_MEM8(0x0B00)
2630#define TCF0_CTRLB  _SFR_MEM8(0x0B01)
2631#define TCF0_CTRLC  _SFR_MEM8(0x0B02)
2632#define TCF0_CTRLD  _SFR_MEM8(0x0B03)
2633#define TCF0_CTRLE  _SFR_MEM8(0x0B04)
2634#define TCF0_INTCTRLA  _SFR_MEM8(0x0B06)
2635#define TCF0_INTCTRLB  _SFR_MEM8(0x0B07)
2636#define TCF0_CTRLFCLR  _SFR_MEM8(0x0B08)
2637#define TCF0_CTRLFSET  _SFR_MEM8(0x0B09)
2638#define TCF0_CTRLGCLR  _SFR_MEM8(0x0B0A)
2639#define TCF0_CTRLGSET  _SFR_MEM8(0x0B0B)
2640#define TCF0_INTFLAGS  _SFR_MEM8(0x0B0C)
2641#define TCF0_TEMP  _SFR_MEM8(0x0B0F)
2642#define TCF0_CNT  _SFR_MEM16(0x0B20)
2643#define TCF0_PER  _SFR_MEM16(0x0B26)
2644#define TCF0_CCA  _SFR_MEM16(0x0B28)
2645#define TCF0_CCB  _SFR_MEM16(0x0B2A)
2646#define TCF0_CCC  _SFR_MEM16(0x0B2C)
2647#define TCF0_CCD  _SFR_MEM16(0x0B2E)
2648#define TCF0_PERBUF  _SFR_MEM16(0x0B36)
2649#define TCF0_CCABUF  _SFR_MEM16(0x0B38)
2650#define TCF0_CCBBUF  _SFR_MEM16(0x0B3A)
2651#define TCF0_CCCBUF  _SFR_MEM16(0x0B3C)
2652#define TCF0_CCDBUF  _SFR_MEM16(0x0B3E)
2653
2654
2655
2656/*================== Bitfield Definitions ================== */
2657
2658/* XOCD - On-Chip Debug System */
2659/* OCD.OCDR0  bit masks and bit positions */
2660#define OCD_OCDRD_gm  0xFF  /* OCDR Dirty group mask. */
2661#define OCD_OCDRD_gp  0  /* OCDR Dirty group position. */
2662#define OCD_OCDRD0_bm  (1<<0)  /* OCDR Dirty bit 0 mask. */
2663#define OCD_OCDRD0_bp  0  /* OCDR Dirty bit 0 position. */
2664#define OCD_OCDRD1_bm  (1<<1)  /* OCDR Dirty bit 1 mask. */
2665#define OCD_OCDRD1_bp  1  /* OCDR Dirty bit 1 position. */
2666#define OCD_OCDRD2_bm  (1<<2)  /* OCDR Dirty bit 2 mask. */
2667#define OCD_OCDRD2_bp  2  /* OCDR Dirty bit 2 position. */
2668#define OCD_OCDRD3_bm  (1<<3)  /* OCDR Dirty bit 3 mask. */
2669#define OCD_OCDRD3_bp  3  /* OCDR Dirty bit 3 position. */
2670#define OCD_OCDRD4_bm  (1<<4)  /* OCDR Dirty bit 4 mask. */
2671#define OCD_OCDRD4_bp  4  /* OCDR Dirty bit 4 position. */
2672#define OCD_OCDRD5_bm  (1<<5)  /* OCDR Dirty bit 5 mask. */
2673#define OCD_OCDRD5_bp  5  /* OCDR Dirty bit 5 position. */
2674#define OCD_OCDRD6_bm  (1<<6)  /* OCDR Dirty bit 6 mask. */
2675#define OCD_OCDRD6_bp  6  /* OCDR Dirty bit 6 position. */
2676#define OCD_OCDRD7_bm  (1<<7)  /* OCDR Dirty bit 7 mask. */
2677#define OCD_OCDRD7_bp  7  /* OCDR Dirty bit 7 position. */
2678
2679/* OCD.OCDR1  bit masks and bit positions */
2680/* OCD_OCDRD  Predefined. */
2681/* OCD_OCDRD  Predefined. */
2682
2683/* CPU - CPU */
2684/* CPU.CCP  bit masks and bit positions */
2685#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
2686#define CPU_CCP_gp  0  /* CCP signature group position. */
2687#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
2688#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
2689#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
2690#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
2691#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
2692#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
2693#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
2694#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
2695#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
2696#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
2697#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
2698#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
2699#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
2700#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
2701#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
2702#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
2703
2704/* CPU.SREG  bit masks and bit positions */
2705#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
2706#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
2707
2708#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
2709#define CPU_T_bp  6  /* Transfer Bit bit position. */
2710
2711#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
2712#define CPU_H_bp  5  /* Half Carry Flag bit position. */
2713
2714#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
2715#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
2716
2717#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
2718#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
2719
2720#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
2721#define CPU_N_bp  2  /* Negative Flag bit position. */
2722
2723#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
2724#define CPU_Z_bp  1  /* Zero Flag bit position. */
2725
2726#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
2727#define CPU_C_bp  0  /* Carry Flag bit position. */
2728
2729/* CLK - Clock System */
2730/* CLK.CTRL  bit masks and bit positions */
2731#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
2732#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
2733#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
2734#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
2735#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
2736#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
2737#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
2738#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
2739
2740/* CLK.PSCTRL  bit masks and bit positions */
2741#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
2742#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
2743#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
2744#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
2745#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
2746#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
2747#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
2748#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
2749#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
2750#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
2751#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
2752#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
2753
2754#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
2755#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
2756#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
2757#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
2758#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
2759#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
2760
2761/* CLK.LOCK  bit masks and bit positions */
2762#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
2763#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
2764
2765/* CLK.RTCCTRL  bit masks and bit positions */
2766#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
2767#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
2768#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
2769#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
2770#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
2771#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
2772#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
2773#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
2774
2775#define CLK_RTCEN_bm  0x01  /* Clock Source Enable bit mask. */
2776#define CLK_RTCEN_bp  0  /* Clock Source Enable bit position. */
2777
2778/* PR.PRGEN  bit masks and bit positions */
2779#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
2780#define PR_RTC_bp  2  /* Real-time Counter bit position. */
2781
2782#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
2783#define PR_EVSYS_bp  1  /* Event System bit position. */
2784
2785/* PR.PRPA  bit masks and bit positions */
2786#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
2787#define PR_ADC_bp  1  /* Port A ADC bit position. */
2788
2789#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
2790#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
2791
2792/* PR.PRPC  bit masks and bit positions */
2793#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
2794#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
2795
2796#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
2797#define PR_USART0_bp  4  /* Port C USART0 bit position. */
2798
2799#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
2800#define PR_SPI_bp  3  /* Port C SPI bit position. */
2801
2802#define PR_HIRES_bm  0x04  /* Port C HIRES bit mask. */
2803#define PR_HIRES_bp  2  /* Port C HIRES bit position. */
2804
2805#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
2806#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
2807
2808#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
2809#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
2810
2811/* PR.PRPD  bit masks and bit positions */
2812/* PR_USART0  Predefined. */
2813/* PR_USART0  Predefined. */
2814
2815/* PR_SPI  Predefined. */
2816/* PR_SPI  Predefined. */
2817
2818/* PR_TC0  Predefined. */
2819/* PR_TC0  Predefined. */
2820
2821/* PR.PRPE  bit masks and bit positions */
2822/* PR_TWI  Predefined. */
2823/* PR_TWI  Predefined. */
2824
2825/* PR_USART0  Predefined. */
2826/* PR_USART0  Predefined. */
2827
2828/* PR_TC0  Predefined. */
2829/* PR_TC0  Predefined. */
2830
2831/* PR.PRPF  bit masks and bit positions */
2832/* PR_USART0  Predefined. */
2833/* PR_USART0  Predefined. */
2834
2835/* PR_TC0  Predefined. */
2836/* PR_TC0  Predefined. */
2837
2838/* SLEEP - Sleep Controller */
2839/* SLEEP.CTRL  bit masks and bit positions */
2840#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
2841#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
2842#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
2843#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
2844#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
2845#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
2846#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
2847#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
2848
2849#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
2850#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
2851
2852/* OSC - Oscillator */
2853/* OSC.CTRL  bit masks and bit positions */
2854#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
2855#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
2856
2857#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
2858#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
2859
2860#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
2861#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
2862
2863#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
2864#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
2865
2866#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
2867#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
2868
2869/* OSC.STATUS  bit masks and bit positions */
2870#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
2871#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
2872
2873#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
2874#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
2875
2876#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
2877#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
2878
2879#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
2880#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
2881
2882#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
2883#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
2884
2885/* OSC.XOSCCTRL  bit masks and bit positions */
2886#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
2887#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
2888#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
2889#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
2890#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
2891#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
2892
2893#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
2894#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
2895
2896#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
2897#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
2898#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
2899#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
2900#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
2901#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
2902#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
2903#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
2904#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
2905#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
2906
2907/* OSC.XOSCFAIL  bit masks and bit positions */
2908#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
2909#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
2910
2911#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
2912#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
2913
2914/* OSC.PLLCTRL  bit masks and bit positions */
2915#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
2916#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
2917#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
2918#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
2919#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
2920#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
2921
2922#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
2923#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
2924#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
2925#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
2926#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
2927#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
2928#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
2929#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
2930#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
2931#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
2932#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
2933#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
2934
2935/* OSC.DFLLCTRL  bit masks and bit positions */
2936#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
2937#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
2938
2939#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
2940#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
2941
2942/* DFLL - DFLL */
2943/* DFLL.CTRL  bit masks and bit positions */
2944#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
2945#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
2946
2947/* DFLL.CALA  bit masks and bit positions */
2948#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
2949#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
2950#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
2951#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
2952#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
2953#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
2954#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
2955#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
2956#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
2957#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
2958#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
2959#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
2960#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
2961#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
2962#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
2963#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
2964
2965/* DFLL.CALB  bit masks and bit positions */
2966#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
2967#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
2968#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
2969#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
2970#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
2971#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
2972#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
2973#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
2974#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
2975#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
2976#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
2977#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
2978#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
2979#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
2980
2981/* RST - Reset */
2982/* RST.STATUS  bit masks and bit positions */
2983#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
2984#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
2985
2986#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
2987#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
2988
2989#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
2990#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
2991
2992#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
2993#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
2994
2995#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
2996#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
2997
2998#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
2999#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
3000
3001#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
3002#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
3003
3004/* RST.CTRL  bit masks and bit positions */
3005#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
3006#define RST_SWRST_bp  0  /* Software Reset bit position. */
3007
3008/* WDT - Watch-Dog Timer */
3009/* WDT.CTRL  bit masks and bit positions */
3010#define WDT_PER_gm  0x3C  /* Period group mask. */
3011#define WDT_PER_gp  2  /* Period group position. */
3012#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
3013#define WDT_PER0_bp  2  /* Period bit 0 position. */
3014#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
3015#define WDT_PER1_bp  3  /* Period bit 1 position. */
3016#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
3017#define WDT_PER2_bp  4  /* Period bit 2 position. */
3018#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
3019#define WDT_PER3_bp  5  /* Period bit 3 position. */
3020
3021#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
3022#define WDT_ENABLE_bp  1  /* Enable bit position. */
3023
3024#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
3025#define WDT_CEN_bp  0  /* Change Enable bit position. */
3026
3027/* WDT.WINCTRL  bit masks and bit positions */
3028#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
3029#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
3030#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
3031#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
3032#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
3033#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
3034#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
3035#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
3036#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
3037#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
3038
3039#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
3040#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
3041
3042#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
3043#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
3044
3045/* WDT.STATUS  bit masks and bit positions */
3046#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
3047#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
3048
3049/* MCU - MCU Control */
3050/* MCU.MCUCR  bit masks and bit positions */
3051#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
3052#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
3053
3054/* MCU.EVSYSLOCK  bit masks and bit positions */
3055#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
3056#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
3057
3058#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
3059#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
3060
3061/* MCU.AWEXLOCK  bit masks and bit positions */
3062#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
3063#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
3064
3065#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
3066#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
3067
3068/* PMIC - Programmable Multi-level Interrupt Controller */
3069/* PMIC.STATUS  bit masks and bit positions */
3070#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
3071#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
3072
3073#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
3074#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
3075
3076#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
3077#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
3078
3079#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
3080#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
3081
3082/* PMIC.INTPRI  bit masks and bit positions */
3083#define PMIC_INTPRI_gm  0xFF  /* Interrupt Priority group mask. */
3084#define PMIC_INTPRI_gp  0  /* Interrupt Priority group position. */
3085#define PMIC_INTPRI0_bm  (1<<0)  /* Interrupt Priority bit 0 mask. */
3086#define PMIC_INTPRI0_bp  0  /* Interrupt Priority bit 0 position. */
3087#define PMIC_INTPRI1_bm  (1<<1)  /* Interrupt Priority bit 1 mask. */
3088#define PMIC_INTPRI1_bp  1  /* Interrupt Priority bit 1 position. */
3089#define PMIC_INTPRI2_bm  (1<<2)  /* Interrupt Priority bit 2 mask. */
3090#define PMIC_INTPRI2_bp  2  /* Interrupt Priority bit 2 position. */
3091#define PMIC_INTPRI3_bm  (1<<3)  /* Interrupt Priority bit 3 mask. */
3092#define PMIC_INTPRI3_bp  3  /* Interrupt Priority bit 3 position. */
3093#define PMIC_INTPRI4_bm  (1<<4)  /* Interrupt Priority bit 4 mask. */
3094#define PMIC_INTPRI4_bp  4  /* Interrupt Priority bit 4 position. */
3095#define PMIC_INTPRI5_bm  (1<<5)  /* Interrupt Priority bit 5 mask. */
3096#define PMIC_INTPRI5_bp  5  /* Interrupt Priority bit 5 position. */
3097#define PMIC_INTPRI6_bm  (1<<6)  /* Interrupt Priority bit 6 mask. */
3098#define PMIC_INTPRI6_bp  6  /* Interrupt Priority bit 6 position. */
3099#define PMIC_INTPRI7_bm  (1<<7)  /* Interrupt Priority bit 7 mask. */
3100#define PMIC_INTPRI7_bp  7  /* Interrupt Priority bit 7 position. */
3101
3102/* PMIC.CTRL  bit masks and bit positions */
3103#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
3104#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
3105
3106#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
3107#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
3108
3109#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
3110#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
3111
3112#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
3113#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
3114
3115#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
3116#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
3117
3118/* CRC - Cyclic Redundancy Checker */
3119/* CRC.CTRL  bit masks and bit positions */
3120#define CRC_RESET_gm  0xC0  /* Reset group mask. */
3121#define CRC_RESET_gp  6  /* Reset group position. */
3122#define CRC_RESET0_bm  (1<<6)  /* Reset bit 0 mask. */
3123#define CRC_RESET0_bp  6  /* Reset bit 0 position. */
3124#define CRC_RESET1_bm  (1<<7)  /* Reset bit 1 mask. */
3125#define CRC_RESET1_bp  7  /* Reset bit 1 position. */
3126
3127#define CRC_CRC32_bm  0x20  /* CRC Mode bit mask. */
3128#define CRC_CRC32_bp  5  /* CRC Mode bit position. */
3129
3130#define CRC_SOURCE_gm  0x0F  /* Input Source group mask. */
3131#define CRC_SOURCE_gp  0  /* Input Source group position. */
3132#define CRC_SOURCE0_bm  (1<<0)  /* Input Source bit 0 mask. */
3133#define CRC_SOURCE0_bp  0  /* Input Source bit 0 position. */
3134#define CRC_SOURCE1_bm  (1<<1)  /* Input Source bit 1 mask. */
3135#define CRC_SOURCE1_bp  1  /* Input Source bit 1 position. */
3136#define CRC_SOURCE2_bm  (1<<2)  /* Input Source bit 2 mask. */
3137#define CRC_SOURCE2_bp  2  /* Input Source bit 2 position. */
3138#define CRC_SOURCE3_bm  (1<<3)  /* Input Source bit 3 mask. */
3139#define CRC_SOURCE3_bp  3  /* Input Source bit 3 position. */
3140
3141/* CRC.STATUS  bit masks and bit positions */
3142#define CRC_ZERO_bm  0x02  /* Zero detection bit mask. */
3143#define CRC_ZERO_bp  1  /* Zero detection bit position. */
3144
3145#define CRC_BUSY_bm  0x01  /* Busy bit mask. */
3146#define CRC_BUSY_bp  0  /* Busy bit position. */
3147
3148/* EVSYS - Event System */
3149/* EVSYS.CH0MUX  bit masks and bit positions */
3150#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
3151#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
3152#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
3153#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
3154#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
3155#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
3156#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
3157#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
3158#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
3159#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
3160#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
3161#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
3162#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
3163#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
3164#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
3165#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
3166#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
3167#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
3168
3169/* EVSYS.CH1MUX  bit masks and bit positions */
3170/* EVSYS_CHMUX  Predefined. */
3171/* EVSYS_CHMUX  Predefined. */
3172
3173/* EVSYS.CH2MUX  bit masks and bit positions */
3174/* EVSYS_CHMUX  Predefined. */
3175/* EVSYS_CHMUX  Predefined. */
3176
3177/* EVSYS.CH3MUX  bit masks and bit positions */
3178/* EVSYS_CHMUX  Predefined. */
3179/* EVSYS_CHMUX  Predefined. */
3180
3181/* EVSYS.CH0CTRL  bit masks and bit positions */
3182#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
3183#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
3184#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
3185#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
3186#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
3187#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
3188
3189#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
3190#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
3191
3192#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
3193#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
3194
3195#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
3196#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
3197#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
3198#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
3199#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
3200#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
3201#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
3202#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
3203
3204/* EVSYS.CH1CTRL  bit masks and bit positions */
3205/* EVSYS_DIGFILT  Predefined. */
3206/* EVSYS_DIGFILT  Predefined. */
3207
3208/* EVSYS.CH2CTRL  bit masks and bit positions */
3209/* EVSYS_DIGFILT  Predefined. */
3210/* EVSYS_DIGFILT  Predefined. */
3211
3212/* EVSYS.CH3CTRL  bit masks and bit positions */
3213/* EVSYS_DIGFILT  Predefined. */
3214/* EVSYS_DIGFILT  Predefined. */
3215
3216/* NVM - Non Volatile Memory Controller */
3217/* NVM.CMD  bit masks and bit positions */
3218#define NVM_CMD_gm  0xFF  /* Command group mask. */
3219#define NVM_CMD_gp  0  /* Command group position. */
3220#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
3221#define NVM_CMD0_bp  0  /* Command bit 0 position. */
3222#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
3223#define NVM_CMD1_bp  1  /* Command bit 1 position. */
3224#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
3225#define NVM_CMD2_bp  2  /* Command bit 2 position. */
3226#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
3227#define NVM_CMD3_bp  3  /* Command bit 3 position. */
3228#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
3229#define NVM_CMD4_bp  4  /* Command bit 4 position. */
3230#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
3231#define NVM_CMD5_bp  5  /* Command bit 5 position. */
3232#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
3233#define NVM_CMD6_bp  6  /* Command bit 6 position. */
3234#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
3235#define NVM_CMD7_bp  7  /* Command bit 7 position. */
3236
3237/* NVM.CTRLA  bit masks and bit positions */
3238#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
3239#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
3240
3241/* NVM.CTRLB  bit masks and bit positions */
3242#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
3243#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
3244
3245#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
3246#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
3247
3248#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
3249#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
3250
3251#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
3252#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
3253
3254/* NVM.INTCTRL  bit masks and bit positions */
3255#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
3256#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
3257#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
3258#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
3259#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
3260#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
3261
3262#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
3263#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
3264#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
3265#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
3266#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
3267#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
3268
3269/* NVM.STATUS  bit masks and bit positions */
3270#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
3271#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
3272
3273#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
3274#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
3275
3276#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
3277#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
3278
3279#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
3280#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
3281
3282/* NVM.LOCKBITS  bit masks and bit positions */
3283#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3284#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3285#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3286#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3287#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3288#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3289
3290#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3291#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3292#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3293#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3294#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3295#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3296
3297#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3298#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3299#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3300#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3301#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3302#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3303
3304#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
3305#define NVM_LB_gp  0  /* Lock Bits group position. */
3306#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3307#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
3308#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3309#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
3310
3311/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
3312#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3313#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3314#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3315#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3316#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3317#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3318
3319#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3320#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3321#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3322#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3323#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3324#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3325
3326#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3327#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3328#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3329#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3330#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3331#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3332
3333#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
3334#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
3335#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3336#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
3337#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3338#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
3339
3340/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
3341#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
3342#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
3343#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
3344#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
3345#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
3346#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
3347#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
3348#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
3349#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
3350#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
3351
3352#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
3353#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
3354#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
3355#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
3356#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
3357#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
3358#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
3359#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
3360#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
3361#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
3362
3363/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
3364#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
3365#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
3366
3367#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
3368#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
3369
3370#define NVM_FUSES_TOSCSEL_bm  0x20  /* 32.768kHz Timer Oscillator Pin Selection bit mask. */
3371#define NVM_FUSES_TOSCSEL_bp  5  /* 32.768kHz Timer Oscillator Pin Selection bit position. */
3372
3373#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
3374#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
3375#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
3376#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
3377#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
3378#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
3379
3380/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
3381#define NVM_FUSES_RSTDISBL_bm  0x10  /* External Reset Disable bit mask. */
3382#define NVM_FUSES_RSTDISBL_bp  4  /* External Reset Disable bit position. */
3383
3384#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
3385#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
3386#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
3387#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
3388#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
3389#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
3390
3391#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
3392#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
3393
3394/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
3395#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
3396#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
3397#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
3398#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
3399#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
3400#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
3401
3402#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
3403#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
3404
3405#define NVM_FUSES_BODLVL_gm  0x07  /* Brownout Detection Voltage Level group mask. */
3406#define NVM_FUSES_BODLVL_gp  0  /* Brownout Detection Voltage Level group position. */
3407#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brownout Detection Voltage Level bit 0 mask. */
3408#define NVM_FUSES_BODLVL0_bp  0  /* Brownout Detection Voltage Level bit 0 position. */
3409#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brownout Detection Voltage Level bit 1 mask. */
3410#define NVM_FUSES_BODLVL1_bp  1  /* Brownout Detection Voltage Level bit 1 position. */
3411#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brownout Detection Voltage Level bit 2 mask. */
3412#define NVM_FUSES_BODLVL2_bp  2  /* Brownout Detection Voltage Level bit 2 position. */
3413
3414/* AC - Analog Comparator */
3415/* AC.AC0CTRL  bit masks and bit positions */
3416#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
3417#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
3418#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
3419#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
3420#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
3421#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
3422
3423#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
3424#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
3425#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
3426#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
3427#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
3428#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
3429
3430#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
3431#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
3432
3433#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
3434#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
3435#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
3436#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
3437#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
3438#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
3439
3440#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
3441#define AC_ENABLE_bp  0  /* Enable bit position. */
3442
3443/* AC.AC1CTRL  bit masks and bit positions */
3444/* AC_INTMODE  Predefined. */
3445/* AC_INTMODE  Predefined. */
3446
3447/* AC_INTLVL  Predefined. */
3448/* AC_INTLVL  Predefined. */
3449
3450/* AC_HSMODE  Predefined. */
3451/* AC_HSMODE  Predefined. */
3452
3453/* AC_HYSMODE  Predefined. */
3454/* AC_HYSMODE  Predefined. */
3455
3456/* AC_ENABLE  Predefined. */
3457/* AC_ENABLE  Predefined. */
3458
3459/* AC.AC0MUXCTRL  bit masks and bit positions */
3460#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
3461#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
3462#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
3463#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
3464#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
3465#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
3466#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
3467#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
3468
3469#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
3470#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
3471#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
3472#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
3473#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
3474#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
3475#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
3476#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
3477
3478/* AC.AC1MUXCTRL  bit masks and bit positions */
3479/* AC_MUXPOS  Predefined. */
3480/* AC_MUXPOS  Predefined. */
3481
3482/* AC_MUXNEG  Predefined. */
3483/* AC_MUXNEG  Predefined. */
3484
3485/* AC.CTRLA  bit masks and bit positions */
3486#define AC_AC0OUT_bm  0x01  /* Analog Comparator 0 Output Enable bit mask. */
3487#define AC_AC0OUT_bp  0  /* Analog Comparator 0 Output Enable bit position. */
3488
3489/* AC.CTRLB  bit masks and bit positions */
3490#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
3491#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
3492#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
3493#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
3494#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
3495#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
3496#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
3497#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
3498#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
3499#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
3500#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
3501#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
3502#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
3503#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
3504
3505/* AC.WINCTRL  bit masks and bit positions */
3506#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
3507#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
3508
3509#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
3510#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
3511#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
3512#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
3513#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
3514#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
3515
3516#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
3517#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
3518#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
3519#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
3520#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
3521#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
3522
3523/* AC.STATUS  bit masks and bit positions */
3524#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
3525#define AC_WSTATE_gp  6  /* Window Mode State group position. */
3526#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
3527#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
3528#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
3529#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
3530
3531#define AC_AC1STATE_bm  0x20  /* Analog Comparator 1 State bit mask. */
3532#define AC_AC1STATE_bp  5  /* Analog Comparator 1 State bit position. */
3533
3534#define AC_AC0STATE_bm  0x10  /* Analog Comparator 0 State bit mask. */
3535#define AC_AC0STATE_bp  4  /* Analog Comparator 0 State bit position. */
3536
3537#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
3538#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
3539
3540#define AC_AC1IF_bm  0x02  /* Analog Comparator 1 Interrupt Flag bit mask. */
3541#define AC_AC1IF_bp  1  /* Analog Comparator 1 Interrupt Flag bit position. */
3542
3543#define AC_AC0IF_bm  0x01  /* Analog Comparator 0 Interrupt Flag bit mask. */
3544#define AC_AC0IF_bp  0  /* Analog Comparator 0 Interrupt Flag bit position. */
3545
3546/* ADC - Analog/Digital Converter */
3547/* ADC_CH.CTRL  bit masks and bit positions */
3548#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
3549#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
3550
3551#define ADC_CH_GAIN_gm  0x1C  /* Gain Factor group mask. */
3552#define ADC_CH_GAIN_gp  2  /* Gain Factor group position. */
3553#define ADC_CH_GAIN0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
3554#define ADC_CH_GAIN0_bp  2  /* Gain Factor bit 0 position. */
3555#define ADC_CH_GAIN1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
3556#define ADC_CH_GAIN1_bp  3  /* Gain Factor bit 1 position. */
3557#define ADC_CH_GAIN2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
3558#define ADC_CH_GAIN2_bp  4  /* Gain Factor bit 2 position. */
3559
3560#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
3561#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
3562#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
3563#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
3564#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
3565#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
3566
3567/* ADC_CH.MUXCTRL  bit masks and bit positions */
3568#define ADC_CH_MUXPOS_gm  0x78  /* MUX selection on Positive ADC input group mask. */
3569#define ADC_CH_MUXPOS_gp  3  /* MUX selection on Positive ADC input group position. */
3570#define ADC_CH_MUXPOS0_bm  (1<<3)  /* MUX selection on Positive ADC input bit 0 mask. */
3571#define ADC_CH_MUXPOS0_bp  3  /* MUX selection on Positive ADC input bit 0 position. */
3572#define ADC_CH_MUXPOS1_bm  (1<<4)  /* MUX selection on Positive ADC input bit 1 mask. */
3573#define ADC_CH_MUXPOS1_bp  4  /* MUX selection on Positive ADC input bit 1 position. */
3574#define ADC_CH_MUXPOS2_bm  (1<<5)  /* MUX selection on Positive ADC input bit 2 mask. */
3575#define ADC_CH_MUXPOS2_bp  5  /* MUX selection on Positive ADC input bit 2 position. */
3576#define ADC_CH_MUXPOS3_bm  (1<<6)  /* MUX selection on Positive ADC input bit 3 mask. */
3577#define ADC_CH_MUXPOS3_bp  6  /* MUX selection on Positive ADC input bit 3 position. */
3578
3579#define ADC_CH_MUXINT_gm  0x78  /* MUX selection on Internal ADC input group mask. */
3580#define ADC_CH_MUXINT_gp  3  /* MUX selection on Internal ADC input group position. */
3581#define ADC_CH_MUXINT0_bm  (1<<3)  /* MUX selection on Internal ADC input bit 0 mask. */
3582#define ADC_CH_MUXINT0_bp  3  /* MUX selection on Internal ADC input bit 0 position. */
3583#define ADC_CH_MUXINT1_bm  (1<<4)  /* MUX selection on Internal ADC input bit 1 mask. */
3584#define ADC_CH_MUXINT1_bp  4  /* MUX selection on Internal ADC input bit 1 position. */
3585#define ADC_CH_MUXINT2_bm  (1<<5)  /* MUX selection on Internal ADC input bit 2 mask. */
3586#define ADC_CH_MUXINT2_bp  5  /* MUX selection on Internal ADC input bit 2 position. */
3587#define ADC_CH_MUXINT3_bm  (1<<6)  /* MUX selection on Internal ADC input bit 3 mask. */
3588#define ADC_CH_MUXINT3_bp  6  /* MUX selection on Internal ADC input bit 3 position. */
3589
3590#define ADC_CH_MUXNEG_gm  0x03  /* MUX selection on Negative ADC input group mask. */
3591#define ADC_CH_MUXNEG_gp  0  /* MUX selection on Negative ADC input group position. */
3592#define ADC_CH_MUXNEG0_bm  (1<<0)  /* MUX selection on Negative ADC input bit 0 mask. */
3593#define ADC_CH_MUXNEG0_bp  0  /* MUX selection on Negative ADC input bit 0 position. */
3594#define ADC_CH_MUXNEG1_bm  (1<<1)  /* MUX selection on Negative ADC input bit 1 mask. */
3595#define ADC_CH_MUXNEG1_bp  1  /* MUX selection on Negative ADC input bit 1 position. */
3596
3597/* ADC_CH.INTCTRL  bit masks and bit positions */
3598#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
3599#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
3600#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
3601#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
3602#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
3603#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
3604
3605#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
3606#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
3607#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
3608#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
3609#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
3610#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
3611
3612/* ADC_CH.INTFLAGS  bit masks and bit positions */
3613#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
3614#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
3615
3616/* ADC_CH.SCAN  bit masks and bit positions */
3617#define ADC_CH_OFFSET_gm  0xF0  /* Positive MUX setting offset group mask. */
3618#define ADC_CH_OFFSET_gp  4  /* Positive MUX setting offset group position. */
3619#define ADC_CH_OFFSET0_bm  (1<<4)  /* Positive MUX setting offset bit 0 mask. */
3620#define ADC_CH_OFFSET0_bp  4  /* Positive MUX setting offset bit 0 position. */
3621#define ADC_CH_OFFSET1_bm  (1<<5)  /* Positive MUX setting offset bit 1 mask. */
3622#define ADC_CH_OFFSET1_bp  5  /* Positive MUX setting offset bit 1 position. */
3623#define ADC_CH_OFFSET2_bm  (1<<6)  /* Positive MUX setting offset bit 2 mask. */
3624#define ADC_CH_OFFSET2_bp  6  /* Positive MUX setting offset bit 2 position. */
3625#define ADC_CH_OFFSET3_bm  (1<<7)  /* Positive MUX setting offset bit 3 mask. */
3626#define ADC_CH_OFFSET3_bp  7  /* Positive MUX setting offset bit 3 position. */
3627
3628#define ADC_CH_SCANNUM_gm  0x0F  /* Number of Channels included in scan group mask. */
3629#define ADC_CH_SCANNUM_gp  0  /* Number of Channels included in scan group position. */
3630#define ADC_CH_SCANNUM0_bm  (1<<0)  /* Number of Channels included in scan bit 0 mask. */
3631#define ADC_CH_SCANNUM0_bp  0  /* Number of Channels included in scan bit 0 position. */
3632#define ADC_CH_SCANNUM1_bm  (1<<1)  /* Number of Channels included in scan bit 1 mask. */
3633#define ADC_CH_SCANNUM1_bp  1  /* Number of Channels included in scan bit 1 position. */
3634#define ADC_CH_SCANNUM2_bm  (1<<2)  /* Number of Channels included in scan bit 2 mask. */
3635#define ADC_CH_SCANNUM2_bp  2  /* Number of Channels included in scan bit 2 position. */
3636#define ADC_CH_SCANNUM3_bm  (1<<3)  /* Number of Channels included in scan bit 3 mask. */
3637#define ADC_CH_SCANNUM3_bp  3  /* Number of Channels included in scan bit 3 position. */
3638
3639/* ADC.CTRLA  bit masks and bit positions */
3640#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
3641#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
3642
3643#define ADC_FLUSH_bm  0x02  /* ADC Flush bit mask. */
3644#define ADC_FLUSH_bp  1  /* ADC Flush bit position. */
3645
3646#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
3647#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
3648
3649/* ADC.CTRLB  bit masks and bit positions */
3650#define ADC_CURRLIMIT_gm  0x60  /* Current Limitation group mask. */
3651#define ADC_CURRLIMIT_gp  5  /* Current Limitation group position. */
3652#define ADC_CURRLIMIT0_bm  (1<<5)  /* Current Limitation bit 0 mask. */
3653#define ADC_CURRLIMIT0_bp  5  /* Current Limitation bit 0 position. */
3654#define ADC_CURRLIMIT1_bm  (1<<6)  /* Current Limitation bit 1 mask. */
3655#define ADC_CURRLIMIT1_bp  6  /* Current Limitation bit 1 position. */
3656
3657#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
3658#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
3659
3660#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
3661#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
3662
3663#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
3664#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
3665#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
3666#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
3667#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
3668#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
3669
3670/* ADC.REFCTRL  bit masks and bit positions */
3671#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
3672#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
3673#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
3674#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
3675#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
3676#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
3677#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
3678#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
3679
3680#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
3681#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
3682
3683#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
3684#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
3685
3686/* ADC.EVCTRL  bit masks and bit positions */
3687#define ADC_EVSEL_gm  0x18  /* Event Input Select group mask. */
3688#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
3689#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
3690#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
3691#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
3692#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
3693
3694#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
3695#define ADC_EVACT_gp  0  /* Event Action Select group position. */
3696#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
3697#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
3698#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
3699#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
3700#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
3701#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
3702
3703/* ADC.PRESCALER  bit masks and bit positions */
3704#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
3705#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
3706#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
3707#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
3708#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
3709#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
3710#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
3711#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
3712
3713/* ADC.INTFLAGS  bit masks and bit positions */
3714#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
3715#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
3716
3717/* RTC - Real-Time Counter */
3718/* RTC.CTRL  bit masks and bit positions */
3719#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
3720#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
3721#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
3722#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
3723#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
3724#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
3725#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
3726#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
3727
3728/* RTC.STATUS  bit masks and bit positions */
3729#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
3730#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
3731
3732/* RTC.INTCTRL  bit masks and bit positions */
3733#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
3734#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
3735#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
3736#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
3737#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
3738#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
3739
3740#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
3741#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
3742#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
3743#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
3744#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
3745#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
3746
3747/* RTC.INTFLAGS  bit masks and bit positions */
3748#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
3749#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
3750
3751#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
3752#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
3753
3754/* TWI - Two-Wire Interface */
3755/* TWI_MASTER.CTRLA  bit masks and bit positions */
3756#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
3757#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
3758#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
3759#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
3760#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
3761#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
3762
3763#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
3764#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
3765
3766#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
3767#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
3768
3769#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
3770#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
3771
3772/* TWI_MASTER.CTRLB  bit masks and bit positions */
3773#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Tisdahmeout group mask. */
3774#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Tisdahmeout group position. */
3775#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Tisdahmeout bit 0 mask. */
3776#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Tisdahmeout bit 0 position. */
3777#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Tisdahmeout bit 1 mask. */
3778#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Tisdahmeout bit 1 position. */
3779
3780#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
3781#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
3782
3783#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
3784#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
3785
3786/* TWI_MASTER.CTRLC  bit masks and bit positions */
3787#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
3788#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
3789
3790#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
3791#define TWI_MASTER_CMD_gp  0  /* Command group position. */
3792#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
3793#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
3794#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
3795#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
3796
3797/* TWI_MASTER.STATUS  bit masks and bit positions */
3798#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
3799#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
3800
3801#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
3802#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
3803
3804#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
3805#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
3806
3807#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
3808#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
3809
3810#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
3811#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
3812
3813#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
3814#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
3815
3816#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
3817#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
3818#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
3819#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
3820#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
3821#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
3822
3823/* TWI_SLAVE.CTRLA  bit masks and bit positions */
3824#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
3825#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
3826#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
3827#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
3828#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
3829#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
3830
3831#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
3832#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
3833
3834#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
3835#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
3836
3837#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
3838#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
3839
3840#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
3841#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
3842
3843#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
3844#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
3845
3846#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
3847#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
3848
3849/* TWI_SLAVE.CTRLB  bit masks and bit positions */
3850#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
3851#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
3852
3853#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
3854#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
3855#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
3856#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
3857#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
3858#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
3859
3860/* TWI_SLAVE.STATUS  bit masks and bit positions */
3861#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
3862#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
3863
3864#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
3865#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
3866
3867#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
3868#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
3869
3870#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
3871#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
3872
3873#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
3874#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
3875
3876#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
3877#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
3878
3879#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
3880#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
3881
3882#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
3883#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
3884
3885/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
3886#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
3887#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
3888#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
3889#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
3890#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
3891#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
3892#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
3893#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
3894#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
3895#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
3896#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
3897#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
3898#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
3899#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
3900#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
3901#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
3902
3903#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
3904#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
3905
3906/* TWI.CTRL  bit masks and bit positions */
3907#define TWI_SDAHOLD_gm  0x06  /* SDA Hold Time Enable group mask. */
3908#define TWI_SDAHOLD_gp  1  /* SDA Hold Time Enable group position. */
3909#define TWI_SDAHOLD0_bm  (1<<1)  /* SDA Hold Time Enable bit 0 mask. */
3910#define TWI_SDAHOLD0_bp  1  /* SDA Hold Time Enable bit 0 position. */
3911#define TWI_SDAHOLD1_bm  (1<<2)  /* SDA Hold Time Enable bit 1 mask. */
3912#define TWI_SDAHOLD1_bp  2  /* SDA Hold Time Enable bit 1 position. */
3913
3914#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
3915#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
3916
3917/* PORT - Port Configuration */
3918/* PORTCFG.VPCTRLA  bit masks and bit positions */
3919#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
3920#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
3921#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
3922#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
3923#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
3924#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
3925#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
3926#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
3927#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
3928#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
3929
3930#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
3931#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
3932#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
3933#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
3934#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
3935#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
3936#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
3937#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
3938#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
3939#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
3940
3941/* PORTCFG.VPCTRLB  bit masks and bit positions */
3942#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
3943#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
3944#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
3945#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
3946#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
3947#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
3948#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
3949#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
3950#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
3951#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
3952
3953#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
3954#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
3955#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
3956#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
3957#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
3958#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
3959#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
3960#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
3961#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
3962#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
3963
3964/* PORTCFG.CLKEVOUT  bit masks and bit positions */
3965#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
3966#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
3967#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
3968#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
3969#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
3970#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
3971
3972#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
3973#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
3974#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
3975#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
3976#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
3977#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
3978
3979/* VPORT.INTFLAGS  bit masks and bit positions */
3980#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
3981#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
3982
3983#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
3984#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
3985
3986/* PORT.INTCTRL  bit masks and bit positions */
3987#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
3988#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
3989#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
3990#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
3991#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
3992#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
3993
3994#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
3995#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
3996#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
3997#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
3998#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
3999#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
4000
4001/* PORT.INTFLAGS  bit masks and bit positions */
4002#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4003#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4004
4005#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4006#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4007
4008/* PORT.REMAP  bit masks and bit positions */
4009#define PORT_SPI_bm  0x20  /* SPI Remap bit mask. */
4010#define PORT_SPI_bp  5  /* SPI Remap bit position. */
4011
4012#define PORT_USART0_bm  0x10  /* USART0 Remap bit mask. */
4013#define PORT_USART0_bp  4  /* USART0 Remap bit position. */
4014
4015#define PORT_TC0D_bm  0x08  /* Timer/Counter 0 Output Compare D bit mask. */
4016#define PORT_TC0D_bp  3  /* Timer/Counter 0 Output Compare D bit position. */
4017
4018#define PORT_TC0C_bm  0x04  /* Timer/Counter 0 Output Compare C bit mask. */
4019#define PORT_TC0C_bp  2  /* Timer/Counter 0 Output Compare C bit position. */
4020
4021#define PORT_TC0B_bm  0x02  /* Timer/Counter 0 Output Compare B bit mask. */
4022#define PORT_TC0B_bp  1  /* Timer/Counter 0 Output Compare B bit position. */
4023
4024#define PORT_TC0A_bm  0x01  /* Timer/Counter 0 Output Compare A bit mask. */
4025#define PORT_TC0A_bp  0  /* Timer/Counter 0 Output Compare A bit position. */
4026
4027/* PORT.PIN0CTRL  bit masks and bit positions */
4028#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
4029#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
4030
4031#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
4032#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
4033
4034#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
4035#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
4036#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
4037#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
4038#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
4039#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
4040#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
4041#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
4042
4043#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
4044#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
4045#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
4046#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
4047#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
4048#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
4049#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
4050#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
4051
4052/* PORT.PIN1CTRL  bit masks and bit positions */
4053/* PORT_SRLEN  Predefined. */
4054/* PORT_SRLEN  Predefined. */
4055
4056/* PORT_INVEN  Predefined. */
4057/* PORT_INVEN  Predefined. */
4058
4059/* PORT_OPC  Predefined. */
4060/* PORT_OPC  Predefined. */
4061
4062/* PORT_ISC  Predefined. */
4063/* PORT_ISC  Predefined. */
4064
4065/* PORT.PIN2CTRL  bit masks and bit positions */
4066/* PORT_SRLEN  Predefined. */
4067/* PORT_SRLEN  Predefined. */
4068
4069/* PORT_INVEN  Predefined. */
4070/* PORT_INVEN  Predefined. */
4071
4072/* PORT_OPC  Predefined. */
4073/* PORT_OPC  Predefined. */
4074
4075/* PORT_ISC  Predefined. */
4076/* PORT_ISC  Predefined. */
4077
4078/* PORT.PIN3CTRL  bit masks and bit positions */
4079/* PORT_SRLEN  Predefined. */
4080/* PORT_SRLEN  Predefined. */
4081
4082/* PORT_INVEN  Predefined. */
4083/* PORT_INVEN  Predefined. */
4084
4085/* PORT_OPC  Predefined. */
4086/* PORT_OPC  Predefined. */
4087
4088/* PORT_ISC  Predefined. */
4089/* PORT_ISC  Predefined. */
4090
4091/* PORT.PIN4CTRL  bit masks and bit positions */
4092/* PORT_SRLEN  Predefined. */
4093/* PORT_SRLEN  Predefined. */
4094
4095/* PORT_INVEN  Predefined. */
4096/* PORT_INVEN  Predefined. */
4097
4098/* PORT_OPC  Predefined. */
4099/* PORT_OPC  Predefined. */
4100
4101/* PORT_ISC  Predefined. */
4102/* PORT_ISC  Predefined. */
4103
4104/* PORT.PIN5CTRL  bit masks and bit positions */
4105/* PORT_SRLEN  Predefined. */
4106/* PORT_SRLEN  Predefined. */
4107
4108/* PORT_INVEN  Predefined. */
4109/* PORT_INVEN  Predefined. */
4110
4111/* PORT_OPC  Predefined. */
4112/* PORT_OPC  Predefined. */
4113
4114/* PORT_ISC  Predefined. */
4115/* PORT_ISC  Predefined. */
4116
4117/* PORT.PIN6CTRL  bit masks and bit positions */
4118/* PORT_SRLEN  Predefined. */
4119/* PORT_SRLEN  Predefined. */
4120
4121/* PORT_INVEN  Predefined. */
4122/* PORT_INVEN  Predefined. */
4123
4124/* PORT_OPC  Predefined. */
4125/* PORT_OPC  Predefined. */
4126
4127/* PORT_ISC  Predefined. */
4128/* PORT_ISC  Predefined. */
4129
4130/* PORT.PIN7CTRL  bit masks and bit positions */
4131/* PORT_SRLEN  Predefined. */
4132/* PORT_SRLEN  Predefined. */
4133
4134/* PORT_INVEN  Predefined. */
4135/* PORT_INVEN  Predefined. */
4136
4137/* PORT_OPC  Predefined. */
4138/* PORT_OPC  Predefined. */
4139
4140/* PORT_ISC  Predefined. */
4141/* PORT_ISC  Predefined. */
4142
4143/* TC - 16-bit Timer/Counter With PWM */
4144/* TC0.CTRLA  bit masks and bit positions */
4145#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4146#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
4147#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4148#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4149#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4150#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4151#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4152#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4153#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4154#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4155
4156/* TC0.CTRLB  bit masks and bit positions */
4157#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
4158#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
4159
4160#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
4161#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
4162
4163#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4164#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4165
4166#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4167#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4168
4169#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4170#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
4171#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4172#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4173#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4174#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4175#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4176#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4177
4178/* TC0.CTRLC  bit masks and bit positions */
4179#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
4180#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
4181
4182#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
4183#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
4184
4185#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4186#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
4187
4188#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4189#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
4190
4191/* TC0.CTRLD  bit masks and bit positions */
4192#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
4193#define TC0_EVACT_gp  5  /* Event Action group position. */
4194#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4195#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
4196#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4197#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
4198#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4199#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
4200
4201#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
4202#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
4203
4204#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4205#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
4206#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4207#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4208#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4209#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4210#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4211#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4212#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4213#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4214
4215/* TC0.CTRLE  bit masks and bit positions */
4216#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4217#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
4218
4219/* TC0.INTCTRLA  bit masks and bit positions */
4220#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4221#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4222#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4223#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4224#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4225#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4226
4227#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4228#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4229#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4230#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4231#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4232#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4233
4234/* TC0.INTCTRLB  bit masks and bit positions */
4235#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
4236#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
4237#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
4238#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
4239#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
4240#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
4241
4242#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
4243#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
4244#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
4245#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
4246#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
4247#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
4248
4249#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4250#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4251#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4252#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4253#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4254#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4255
4256#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4257#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4258#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4259#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4260#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4261#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4262
4263/* TC0.CTRLFCLR  bit masks and bit positions */
4264#define TC0_CMD_gm  0x0C  /* Command group mask. */
4265#define TC0_CMD_gp  2  /* Command group position. */
4266#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4267#define TC0_CMD0_bp  2  /* Command bit 0 position. */
4268#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4269#define TC0_CMD1_bp  3  /* Command bit 1 position. */
4270
4271#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
4272#define TC0_LUPD_bp  1  /* Lock Update bit position. */
4273
4274#define TC0_DIR_bm  0x01  /* Direction bit mask. */
4275#define TC0_DIR_bp  0  /* Direction bit position. */
4276
4277/* TC0.CTRLFSET  bit masks and bit positions */
4278/* TC0_CMD  Predefined. */
4279/* TC0_CMD  Predefined. */
4280
4281/* TC0_LUPD  Predefined. */
4282/* TC0_LUPD  Predefined. */
4283
4284/* TC0_DIR  Predefined. */
4285/* TC0_DIR  Predefined. */
4286
4287/* TC0.CTRLGCLR  bit masks and bit positions */
4288#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
4289#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
4290
4291#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
4292#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
4293
4294#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
4295#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
4296
4297#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
4298#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
4299
4300#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
4301#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
4302
4303/* TC0.CTRLGSET  bit masks and bit positions */
4304/* TC0_CCDBV  Predefined. */
4305/* TC0_CCDBV  Predefined. */
4306
4307/* TC0_CCCBV  Predefined. */
4308/* TC0_CCCBV  Predefined. */
4309
4310/* TC0_CCBBV  Predefined. */
4311/* TC0_CCBBV  Predefined. */
4312
4313/* TC0_CCABV  Predefined. */
4314/* TC0_CCABV  Predefined. */
4315
4316/* TC0_PERBV  Predefined. */
4317/* TC0_PERBV  Predefined. */
4318
4319/* TC0.INTFLAGS  bit masks and bit positions */
4320#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
4321#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
4322
4323#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
4324#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
4325
4326#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
4327#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
4328
4329#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
4330#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
4331
4332#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
4333#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
4334
4335#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4336#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4337
4338/* TC1.CTRLA  bit masks and bit positions */
4339#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4340#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
4341#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4342#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4343#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4344#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4345#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4346#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4347#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4348#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4349
4350/* TC1.CTRLB  bit masks and bit positions */
4351#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4352#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4353
4354#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4355#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4356
4357#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4358#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
4359#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4360#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4361#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4362#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4363#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4364#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4365
4366/* TC1.CTRLC  bit masks and bit positions */
4367#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4368#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
4369
4370#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4371#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
4372
4373/* TC1.CTRLD  bit masks and bit positions */
4374#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
4375#define TC1_EVACT_gp  5  /* Event Action group position. */
4376#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4377#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
4378#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4379#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
4380#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4381#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
4382
4383#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
4384#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
4385
4386#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4387#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
4388#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4389#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4390#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4391#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4392#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4393#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4394#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4395#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4396
4397/* TC1.CTRLE  bit masks and bit positions */
4398#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4399#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
4400
4401/* TC1.INTCTRLA  bit masks and bit positions */
4402#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4403#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4404#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4405#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4406#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4407#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4408
4409#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4410#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4411#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4412#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4413#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4414#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4415
4416/* TC1.INTCTRLB  bit masks and bit positions */
4417#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4418#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4419#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4420#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4421#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4422#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4423
4424#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4425#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4426#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4427#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4428#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4429#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4430
4431/* TC1.CTRLFCLR  bit masks and bit positions */
4432#define TC1_CMD_gm  0x0C  /* Command group mask. */
4433#define TC1_CMD_gp  2  /* Command group position. */
4434#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4435#define TC1_CMD0_bp  2  /* Command bit 0 position. */
4436#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4437#define TC1_CMD1_bp  3  /* Command bit 1 position. */
4438
4439#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
4440#define TC1_LUPD_bp  1  /* Lock Update bit position. */
4441
4442#define TC1_DIR_bm  0x01  /* Direction bit mask. */
4443#define TC1_DIR_bp  0  /* Direction bit position. */
4444
4445/* TC1.CTRLFSET  bit masks and bit positions */
4446/* TC1_CMD  Predefined. */
4447/* TC1_CMD  Predefined. */
4448
4449/* TC1_LUPD  Predefined. */
4450/* TC1_LUPD  Predefined. */
4451
4452/* TC1_DIR  Predefined. */
4453/* TC1_DIR  Predefined. */
4454
4455/* TC1.CTRLGCLR  bit masks and bit positions */
4456#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
4457#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
4458
4459#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
4460#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
4461
4462#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
4463#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
4464
4465/* TC1.CTRLGSET  bit masks and bit positions */
4466/* TC1_CCBBV  Predefined. */
4467/* TC1_CCBBV  Predefined. */
4468
4469/* TC1_CCABV  Predefined. */
4470/* TC1_CCABV  Predefined. */
4471
4472/* TC1_PERBV  Predefined. */
4473/* TC1_PERBV  Predefined. */
4474
4475/* TC1.INTFLAGS  bit masks and bit positions */
4476#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
4477#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
4478
4479#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
4480#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
4481
4482#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
4483#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
4484
4485#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4486#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4487
4488/* AWEX.CTRL  bit masks and bit positions */
4489#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
4490#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
4491
4492#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
4493#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
4494
4495#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
4496#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
4497
4498#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
4499#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
4500
4501#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
4502#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
4503
4504#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
4505#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
4506
4507/* AWEX.FDCTRL  bit masks and bit positions */
4508#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
4509#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
4510
4511#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
4512#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
4513
4514#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
4515#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
4516#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
4517#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
4518#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
4519#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
4520
4521/* AWEX.STATUS  bit masks and bit positions */
4522#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
4523#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
4524
4525#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
4526#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
4527
4528#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
4529#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
4530
4531/* HIRES.CTRLA  bit masks and bit positions */
4532#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
4533#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
4534#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
4535#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
4536#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
4537#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
4538
4539/* USART - Universal Asynchronous Receiver-Transmitter */
4540/* USART.STATUS  bit masks and bit positions */
4541#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
4542#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
4543
4544#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
4545#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
4546
4547#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
4548#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
4549
4550#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
4551#define USART_FERR_bp  4  /* Frame Error bit position. */
4552
4553#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
4554#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
4555
4556#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
4557#define USART_PERR_bp  2  /* Parity Error bit position. */
4558
4559#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
4560#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
4561
4562/* USART.CTRLA  bit masks and bit positions */
4563#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
4564#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
4565#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
4566#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
4567#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
4568#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
4569
4570#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
4571#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
4572#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
4573#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
4574#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
4575#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
4576
4577#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
4578#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
4579#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
4580#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
4581#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
4582#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
4583
4584/* USART.CTRLB  bit masks and bit positions */
4585#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
4586#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
4587
4588#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
4589#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
4590
4591#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
4592#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
4593
4594#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
4595#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
4596
4597#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
4598#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
4599
4600/* USART.CTRLC  bit masks and bit positions */
4601#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
4602#define USART_CMODE_gp  6  /* Communication Mode group position. */
4603#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
4604#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
4605#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
4606#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
4607
4608#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
4609#define USART_PMODE_gp  4  /* Parity Mode group position. */
4610#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
4611#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
4612#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
4613#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
4614
4615#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
4616#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
4617
4618#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
4619#define USART_CHSIZE_gp  0  /* Character Size group position. */
4620#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
4621#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
4622#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
4623#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
4624#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
4625#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
4626
4627#define USART_UDORD_bm  0x04  /* SPI Master Mode, Data Order bit mask. */
4628#define USART_UDORD_bp  2  /* SPI Master Mode, Data Order bit position. */
4629
4630#define USART_UCPHA_bm  0x02  /* SPI Master Mode, Clock Phase bit mask. */
4631#define USART_UCPHA_bp  1  /* SPI Master Mode, Clock Phase bit position. */
4632
4633/* USART.BAUDCTRLA  bit masks and bit positions */
4634#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
4635#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
4636#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
4637#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
4638#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
4639#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
4640#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
4641#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
4642#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
4643#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
4644#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
4645#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
4646#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
4647#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
4648#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
4649#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
4650#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
4651#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
4652
4653/* USART.BAUDCTRLB  bit masks and bit positions */
4654#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
4655#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
4656#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
4657#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
4658#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
4659#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
4660#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
4661#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
4662#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
4663#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
4664
4665/* USART_BSEL  Predefined. */
4666/* USART_BSEL  Predefined. */
4667
4668/* SPI - Serial Peripheral Interface */
4669/* SPI.CTRL  bit masks and bit positions */
4670#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
4671#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
4672
4673#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
4674#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
4675
4676#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
4677#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
4678
4679#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
4680#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
4681
4682#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
4683#define SPI_MODE_gp  2  /* SPI Mode group position. */
4684#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
4685#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
4686#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
4687#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
4688
4689#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
4690#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
4691#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
4692#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
4693#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
4694#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
4695
4696/* SPI.INTCTRL  bit masks and bit positions */
4697#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
4698#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
4699#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
4700#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
4701#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
4702#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
4703
4704/* SPI.STATUS  bit masks and bit positions */
4705#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
4706#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
4707
4708#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
4709#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
4710
4711/* IRCOM - IR Communication Module */
4712/* IRCOM.CTRL  bit masks and bit positions */
4713#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
4714#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
4715#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
4716#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
4717#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
4718#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
4719#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
4720#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
4721#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
4722#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
4723
4724
4725
4726// Generic Port Pins
4727
4728#define PIN0_bm 0x01
4729#define PIN0_bp 0
4730#define PIN1_bm 0x02
4731#define PIN1_bp 1
4732#define PIN2_bm 0x04
4733#define PIN2_bp 2
4734#define PIN3_bm 0x08
4735#define PIN3_bp 3
4736#define PIN4_bm 0x10
4737#define PIN4_bp 4
4738#define PIN5_bm 0x20
4739#define PIN5_bp 5
4740#define PIN6_bm 0x40
4741#define PIN6_bp 6
4742#define PIN7_bm 0x80
4743#define PIN7_bp 7
4744
4745/* ========== Interrupt Vector Definitions ========== */
4746/* Vector 0 is the reset vector */
4747
4748/* OSC interrupt vectors */
4749#define OSC_OSCF_vect_num  1
4750#define OSC_OSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
4751
4752/* PORTC interrupt vectors */
4753#define PORTC_INT0_vect_num  2
4754#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
4755#define PORTC_INT1_vect_num  3
4756#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
4757
4758/* PORTR interrupt vectors */
4759#define PORTR_INT0_vect_num  4
4760#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
4761#define PORTR_INT1_vect_num  5
4762#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
4763
4764/* RTC interrupt vectors */
4765#define RTC_OVF_vect_num  10
4766#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
4767#define RTC_COMP_vect_num  11
4768#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
4769
4770/* TWIC interrupt vectors */
4771#define TWIC_TWIS_vect_num  12
4772#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
4773#define TWIC_TWIM_vect_num  13
4774#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
4775
4776/* TCC0 interrupt vectors */
4777#define TCC0_OVF_vect_num  14
4778#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
4779#define TCC0_ERR_vect_num  15
4780#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
4781#define TCC0_CCA_vect_num  16
4782#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
4783#define TCC0_CCB_vect_num  17
4784#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
4785#define TCC0_CCC_vect_num  18
4786#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
4787#define TCC0_CCD_vect_num  19
4788#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
4789
4790/* TCC1 interrupt vectors */
4791#define TCC1_OVF_vect_num  20
4792#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
4793#define TCC1_ERR_vect_num  21
4794#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
4795#define TCC1_CCA_vect_num  22
4796#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
4797#define TCC1_CCB_vect_num  23
4798#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
4799
4800/* SPIC interrupt vectors */
4801#define SPIC_INT_vect_num  24
4802#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
4803
4804/* USARTC0 interrupt vectors */
4805#define USARTC0_RXC_vect_num  25
4806#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
4807#define USARTC0_DRE_vect_num  26
4808#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
4809#define USARTC0_TXC_vect_num  27
4810#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
4811
4812/* NVM interrupt vectors */
4813#define NVM_EE_vect_num  32
4814#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
4815#define NVM_SPM_vect_num  33
4816#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
4817
4818/* PORTB interrupt vectors */
4819#define PORTB_INT0_vect_num  34
4820#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
4821#define PORTB_INT1_vect_num  35
4822#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
4823
4824/* PORTE interrupt vectors */
4825#define PORTE_INT0_vect_num  43
4826#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
4827#define PORTE_INT1_vect_num  44
4828#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
4829
4830/* TWIE interrupt vectors */
4831#define TWIE_TWIS_vect_num  45
4832#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
4833#define TWIE_TWIM_vect_num  46
4834#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
4835
4836/* TCE0 interrupt vectors */
4837#define TCE0_OVF_vect_num  47
4838#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
4839#define TCE0_ERR_vect_num  48
4840#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
4841#define TCE0_CCA_vect_num  49
4842#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
4843#define TCE0_CCB_vect_num  50
4844#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
4845#define TCE0_CCC_vect_num  51
4846#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
4847#define TCE0_CCD_vect_num  52
4848#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
4849
4850/* USARTE0 interrupt vectors */
4851#define USARTE0_RXC_vect_num  58
4852#define USARTE0_RXC_vect      _VECTOR(58)  /* Reception Complete Interrupt */
4853#define USARTE0_DRE_vect_num  59
4854#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
4855#define USARTE0_TXC_vect_num  60
4856#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
4857
4858/* PORTD interrupt vectors */
4859#define PORTD_INT0_vect_num  64
4860#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
4861#define PORTD_INT1_vect_num  65
4862#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
4863
4864/* PORTA interrupt vectors */
4865#define PORTA_INT0_vect_num  66
4866#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
4867#define PORTA_INT1_vect_num  67
4868#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
4869
4870/* ACA interrupt vectors */
4871#define ACA_AC0_vect_num  68
4872#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
4873#define ACA_AC1_vect_num  69
4874#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
4875#define ACA_ACW_vect_num  70
4876#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
4877
4878/* ADCA interrupt vectors */
4879#define ADCA_CH0_vect_num  71
4880#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
4881
4882/* TCD0 interrupt vectors */
4883#define TCD0_OVF_vect_num  77
4884#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
4885#define TCD0_ERR_vect_num  78
4886#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
4887#define TCD0_CCA_vect_num  79
4888#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
4889#define TCD0_CCB_vect_num  80
4890#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
4891#define TCD0_CCC_vect_num  81
4892#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
4893#define TCD0_CCD_vect_num  82
4894#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
4895
4896/* SPID interrupt vectors */
4897#define SPID_INT_vect_num  87
4898#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
4899
4900/* USARTD0 interrupt vectors */
4901#define USARTD0_RXC_vect_num  88
4902#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
4903#define USARTD0_DRE_vect_num  89
4904#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
4905#define USARTD0_TXC_vect_num  90
4906#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
4907
4908/* PORTF interrupt vectors */
4909#define PORTF_INT0_vect_num  104
4910#define PORTF_INT0_vect      _VECTOR(104)  /* External Interrupt 0 */
4911#define PORTF_INT1_vect_num  105
4912#define PORTF_INT1_vect      _VECTOR(105)  /* External Interrupt 1 */
4913
4914/* TCF0 interrupt vectors */
4915#define TCF0_OVF_vect_num  108
4916#define TCF0_OVF_vect      _VECTOR(108)  /* Overflow Interrupt */
4917#define TCF0_ERR_vect_num  109
4918#define TCF0_ERR_vect      _VECTOR(109)  /* Error Interrupt */
4919#define TCF0_CCA_vect_num  110
4920#define TCF0_CCA_vect      _VECTOR(110)  /* Compare or Capture A Interrupt */
4921#define TCF0_CCB_vect_num  111
4922#define TCF0_CCB_vect      _VECTOR(111)  /* Compare or Capture B Interrupt */
4923#define TCF0_CCC_vect_num  112
4924#define TCF0_CCC_vect      _VECTOR(112)  /* Compare or Capture C Interrupt */
4925#define TCF0_CCD_vect_num  113
4926#define TCF0_CCD_vect      _VECTOR(113)  /* Compare or Capture D Interrupt */
4927
4928#define _VECTOR_SIZE 4 /* Size of individual vector. */
4929#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
4930
4931
4932/* ========== Constants ========== */
4933
4934#define PROGMEM_START     (0x0000)
4935#define PROGMEM_SIZE      (36864)
4936#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
4937
4938#define APP_SECTION_START     (0x0000)
4939#define APP_SECTION_SIZE      (32768)
4940#define APP_SECTION_PAGE_SIZE (256)
4941#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
4942
4943#define APPTABLE_SECTION_START     (0x7000)
4944#define APPTABLE_SECTION_SIZE      (4096)
4945#define APPTABLE_SECTION_PAGE_SIZE (256)
4946#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
4947
4948#define BOOT_SECTION_START     (0x8000)
4949#define BOOT_SECTION_SIZE      (4096)
4950#define BOOT_SECTION_PAGE_SIZE (256)
4951#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
4952
4953#define DATAMEM_START     (0x0000)
4954#define DATAMEM_SIZE      (12288)
4955#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
4956
4957#define IO_START     (0x0000)
4958#define IO_SIZE      (4096)
4959#define IO_PAGE_SIZE (0)
4960#define IO_END       (IO_START + IO_SIZE - 1)
4961
4962#define MAPPED_EEPROM_START     (0x1000)
4963#define MAPPED_EEPROM_SIZE      (1024)
4964#define MAPPED_EEPROM_PAGE_SIZE (0)
4965#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
4966
4967#define INTERNAL_SRAM_START     (0x2000)
4968#define INTERNAL_SRAM_SIZE      (4096)
4969#define INTERNAL_SRAM_PAGE_SIZE (0)
4970#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
4971
4972#define EEPROM_START     (0x0000)
4973#define EEPROM_SIZE      (1024)
4974#define EEPROM_PAGE_SIZE (32)
4975#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
4976
4977#define SIGNATURES_START     (0x0000)
4978#define SIGNATURES_SIZE      (3)
4979#define SIGNATURES_PAGE_SIZE (0)
4980#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
4981
4982#define FUSES_START     (0x0000)
4983#define FUSES_SIZE      (6)
4984#define FUSES_PAGE_SIZE (0)
4985#define FUSES_END       (FUSES_START + FUSES_SIZE - 1)
4986
4987#define LOCKBITS_START     (0x0000)
4988#define LOCKBITS_SIZE      (1)
4989#define LOCKBITS_PAGE_SIZE (0)
4990#define LOCKBITS_END       (LOCKBITS_START + LOCKBITS_SIZE - 1)
4991
4992#define USER_SIGNATURES_START     (0x0000)
4993#define USER_SIGNATURES_SIZE      (256)
4994#define USER_SIGNATURES_PAGE_SIZE (256)
4995#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
4996
4997#define PROD_SIGNATURES_START     (0x0000)
4998#define PROD_SIGNATURES_SIZE      (52)
4999#define PROD_SIGNATURES_PAGE_SIZE (256)
5000#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
5001
5002#define FLASHSTART   PROGMEM_START
5003#define FLASHEND     PROGMEM_END
5004#define SPM_PAGESIZE 256
5005#define RAMSTART     INTERNAL_SRAM_START
5006#define RAMSIZE      INTERNAL_SRAM_SIZE
5007#define RAMEND       INTERNAL_SRAM_END
5008#define E2END        EEPROM_END
5009#define E2PAGESIZE   EEPROM_PAGE_SIZE
5010
5011
5012/* ========== Fuses ========== */
5013#define FUSE_MEMORY_SIZE 6
5014
5015/* Fuse Byte 0 Reserved */
5016
5017/* Fuse Byte 1 */
5018#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
5019#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
5020#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
5021#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
5022#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
5023#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
5024#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
5025#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
5026#define FUSE1_DEFAULT  (0xFF)
5027
5028/* Fuse Byte 2 */
5029#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
5030#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
5031#define FUSE_TOSCSEL  (unsigned char)~_BV(5)  /* 32.768kHz Timer Oscillator Pin Selection */
5032#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
5033#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
5034#define FUSE2_DEFAULT  (0xFF)
5035
5036/* Fuse Byte 3 Reserved */
5037
5038/* Fuse Byte 4 */
5039#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
5040#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
5041#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
5042#define FUSE_RSTDISBL  (unsigned char)~_BV(4)  /* External Reset Disable */
5043#define FUSE4_DEFAULT  (0xFF)
5044
5045/* Fuse Byte 5 */
5046#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brownout Detection Voltage Level Bit 0 */
5047#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brownout Detection Voltage Level Bit 1 */
5048#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brownout Detection Voltage Level Bit 2 */
5049#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
5050#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
5051#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
5052#define FUSE5_DEFAULT  (0xFF)
5053
5054/* ========== Lock Bits ========== */
5055#define __LOCK_BITS_EXIST
5056#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
5057#define __BOOT_LOCK_APPLICATION_BITS_EXIST
5058#define __BOOT_LOCK_BOOT_BITS_EXIST
5059
5060/* ========== Signature ========== */
5061#define SIGNATURE_0 0x1E
5062#define SIGNATURE_1 0x95
5063#define SIGNATURE_2 0x4A
5064
5065/* ========== Power Reduction Condition Definitions ========== */
5066
5067/* PR.PRGEN */
5068#define __AVR_HAVE_PRGEN        (PR_RTC_bm|PR_EVSYS_bm)
5069#define __AVR_HAVE_PRGEN_RTC
5070#define __AVR_HAVE_PRGEN_EVSYS
5071
5072/* PR.PRPA */
5073#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm)
5074#define __AVR_HAVE_PRPA_ADC
5075#define __AVR_HAVE_PRPA_AC
5076
5077/* PR.PRPC */
5078#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm)
5079#define __AVR_HAVE_PRPC_TWI
5080#define __AVR_HAVE_PRPC_USART0
5081#define __AVR_HAVE_PRPC_SPI
5082#define __AVR_HAVE_PRPC_HIRES
5083#define __AVR_HAVE_PRPC_TC1
5084#define __AVR_HAVE_PRPC_TC0
5085
5086/* PR.PRPD */
5087#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm)
5088#define __AVR_HAVE_PRPD_USART0
5089#define __AVR_HAVE_PRPD_SPI
5090#define __AVR_HAVE_PRPD_TC0
5091
5092/* PR.PRPE */
5093#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm)
5094#define __AVR_HAVE_PRPE_TWI
5095#define __AVR_HAVE_PRPE_USART0
5096#define __AVR_HAVE_PRPE_TC0
5097
5098/* PR.PRPF */
5099#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm)
5100#define __AVR_HAVE_PRPF_USART0
5101#define __AVR_HAVE_PRPF_TC0
5102
5103
5104#endif /* #ifdef _AVR_ATXMEGA32D3_H_INCLUDED */
5105
Note: See TracBrowser for help on using the repository browser.