source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/avr/include/avr/iox32d4.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

File size: 240.6 KB
Line 
1/* Copyright (c) 2009-2010 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id: iox32d4.h 2200 2010-12-14 04:24:24Z arcanum $ */
32
33/* avr/iox32d4.h - definitions for ATxmega32D4 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iox32d4.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47
48#ifndef _AVR_ATxmega32D4_H_
49#define _AVR_ATxmega32D4_H_ 1
50
51
52/* Ungrouped common registers */
53#define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
54#define GPIO1  _SFR_MEM8(0x0001)  /* General Purpose IO Register 1 */
55#define GPIO2  _SFR_MEM8(0x0002)  /* General Purpose IO Register 2 */
56#define GPIO3  _SFR_MEM8(0x0003)  /* General Purpose IO Register 3 */
57#define GPIO4  _SFR_MEM8(0x0004)  /* General Purpose IO Register 4 */
58#define GPIO5  _SFR_MEM8(0x0005)  /* General Purpose IO Register 5 */
59#define GPIO6  _SFR_MEM8(0x0006)  /* General Purpose IO Register 6 */
60#define GPIO7  _SFR_MEM8(0x0007)  /* General Purpose IO Register 7 */
61#define GPIO8  _SFR_MEM8(0x0008)  /* General Purpose IO Register 8 */
62#define GPIO9  _SFR_MEM8(0x0009)  /* General Purpose IO Register 9 */
63#define GPIOA  _SFR_MEM8(0x000A)  /* General Purpose IO Register 10 */
64#define GPIOB  _SFR_MEM8(0x000B)  /* General Purpose IO Register 11 */
65#define GPIOC  _SFR_MEM8(0x000C)  /* General Purpose IO Register 12 */
66#define GPIOD  _SFR_MEM8(0x000D)  /* General Purpose IO Register 13 */
67#define GPIOE  _SFR_MEM8(0x000E)  /* General Purpose IO Register 14 */
68#define GPIOF  _SFR_MEM8(0x000F)  /* General Purpose IO Register 15 */
69
70#define CCP  _SFR_MEM8(0x0034)  /* Configuration Change Protection */
71#define RAMPD  _SFR_MEM8(0x0038)  /* Ramp D */
72#define RAMPX  _SFR_MEM8(0x0039)  /* Ramp X */
73#define RAMPY  _SFR_MEM8(0x003A)  /* Ramp Y */
74#define RAMPZ  _SFR_MEM8(0x003B)  /* Ramp Z */
75#define EIND  _SFR_MEM8(0x003C)  /* Extended Indirect Jump */
76#define SPL  _SFR_MEM8(0x003D)  /* Stack Pointer Low */
77#define SPH  _SFR_MEM8(0x003E)  /* Stack Pointer High */
78#define SREG  _SFR_MEM8(0x003F)  /* Status Register */
79
80
81/* C Language Only */
82#if !defined (__ASSEMBLER__)
83
84#include <stdint.h>
85
86typedef volatile uint8_t register8_t;
87typedef volatile uint16_t register16_t;
88typedef volatile uint32_t register32_t;
89
90
91#ifdef _WORDREGISTER
92#undef _WORDREGISTER
93#endif
94#define _WORDREGISTER(regname)   \
95    __extension__ union \
96    { \
97        register16_t regname; \
98        struct \
99        { \
100            register8_t regname ## L; \
101            register8_t regname ## H; \
102        }; \
103    }
104
105#ifdef _DWORDREGISTER
106#undef _DWORDREGISTER
107#endif
108#define _DWORDREGISTER(regname)  \
109   __extension__  union \
110    { \
111        register32_t regname; \
112        struct \
113        { \
114            register8_t regname ## 0; \
115            register8_t regname ## 1; \
116            register8_t regname ## 2; \
117            register8_t regname ## 3; \
118        }; \
119    }
120
121
122/*
123==========================================================================
124IO Module Structures
125==========================================================================
126*/
127
128
129/*
130--------------------------------------------------------------------------
131XOCD - On-Chip Debug System
132--------------------------------------------------------------------------
133*/
134
135/* On-Chip Debug System */
136typedef struct OCD_struct
137{
138    register8_t OCDR0;  /* OCD Register 0 */
139    register8_t OCDR1;  /* OCD Register 1 */
140} OCD_t;
141
142
143/* CCP signatures */
144typedef enum CCP_enum
145{
146    CCP_SPM_gc = (0x9D<<0),  /* SPM Instruction Protection */
147    CCP_IOREG_gc = (0xD8<<0),  /* IO Register Protection */
148} CCP_t;
149
150
151/*
152--------------------------------------------------------------------------
153CLK - Clock System
154--------------------------------------------------------------------------
155*/
156
157/* Clock System */
158typedef struct CLK_struct
159{
160    register8_t CTRL;  /* Control Register */
161    register8_t PSCTRL;  /* Prescaler Control Register */
162    register8_t LOCK;  /* Lock register */
163    register8_t RTCCTRL;  /* RTC Control Register */
164} CLK_t;
165
166/*
167--------------------------------------------------------------------------
168CLK - Clock System
169--------------------------------------------------------------------------
170*/
171
172/* Power Reduction */
173typedef struct PR_struct
174{
175    register8_t PRGEN;  /* General Power Reduction */
176    register8_t PRPA;  /* Power Reduction Port A */
177    register8_t PRPB;  /* Power Reduction Port B */
178    register8_t PRPC;  /* Power Reduction Port C */
179    register8_t PRPD;  /* Power Reduction Port D */
180    register8_t PRPE;  /* Power Reduction Port E */
181    register8_t PRPF;  /* Power Reduction Port F */
182} PR_t;
183
184/* System Clock Selection */
185typedef enum CLK_SCLKSEL_enum
186{
187    CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
188    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
189    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
190    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
191    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
192} CLK_SCLKSEL_t;
193
194/* Prescaler A Division Factor */
195typedef enum CLK_PSADIV_enum
196{
197    CLK_PSADIV_1_gc = (0x00<<2),  /* Divide by 1 */
198    CLK_PSADIV_2_gc = (0x01<<2),  /* Divide by 2 */
199    CLK_PSADIV_4_gc = (0x03<<2),  /* Divide by 4 */
200    CLK_PSADIV_8_gc = (0x05<<2),  /* Divide by 8 */
201    CLK_PSADIV_16_gc = (0x07<<2),  /* Divide by 16 */
202    CLK_PSADIV_32_gc = (0x09<<2),  /* Divide by 32 */
203    CLK_PSADIV_64_gc = (0x0B<<2),  /* Divide by 64 */
204    CLK_PSADIV_128_gc = (0x0D<<2),  /* Divide by 128 */
205    CLK_PSADIV_256_gc = (0x0F<<2),  /* Divide by 256 */
206    CLK_PSADIV_512_gc = (0x11<<2),  /* Divide by 512 */
207} CLK_PSADIV_t;
208
209/* Prescaler B and C Division Factor */
210typedef enum CLK_PSBCDIV_enum
211{
212    CLK_PSBCDIV_1_1_gc = (0x00<<0),  /* Divide B by 1 and C by 1 */
213    CLK_PSBCDIV_1_2_gc = (0x01<<0),  /* Divide B by 1 and C by 2 */
214    CLK_PSBCDIV_4_1_gc = (0x02<<0),  /* Divide B by 4 and C by 1 */
215    CLK_PSBCDIV_2_2_gc = (0x03<<0),  /* Divide B by 2 and C by 2 */
216} CLK_PSBCDIV_t;
217
218/* RTC Clock Source */
219typedef enum CLK_RTCSRC_enum
220{
221    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
222    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
223    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
224    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
225} CLK_RTCSRC_t;
226
227
228/*
229--------------------------------------------------------------------------
230SLEEP - Sleep Controller
231--------------------------------------------------------------------------
232*/
233
234/* Sleep Controller */
235typedef struct SLEEP_struct
236{
237    register8_t CTRL;  /* Control Register */
238} SLEEP_t;
239
240/* Sleep Mode */
241typedef enum SLEEP_SMODE_enum
242{
243    SLEEP_SMODE_IDLE_gc = (0x00<<1),  /* Idle mode */
244    SLEEP_SMODE_PDOWN_gc = (0x02<<1),  /* Power-down Mode */
245    SLEEP_SMODE_PSAVE_gc = (0x03<<1),  /* Power-save Mode */
246    SLEEP_SMODE_STDBY_gc = (0x06<<1),  /* Standby Mode */
247    SLEEP_SMODE_ESTDBY_gc = (0x07<<1),  /* Extended Standby Mode */
248} SLEEP_SMODE_t;
249
250
251/*
252--------------------------------------------------------------------------
253OSC - Oscillator
254--------------------------------------------------------------------------
255*/
256
257/* Oscillator */
258typedef struct OSC_struct
259{
260    register8_t CTRL;  /* Control Register */
261    register8_t STATUS;  /* Status Register */
262    register8_t XOSCCTRL;  /* External Oscillator Control Register */
263    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
264    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
265    register8_t PLLCTRL;  /* PLL Control REgister */
266    register8_t DFLLCTRL;  /* DFLL Control Register */
267} OSC_t;
268
269/* Oscillator Frequency Range */
270typedef enum OSC_FRQRANGE_enum
271{
272    OSC_FRQRANGE_04TO2_gc = (0x00<<6),  /* 0.4 - 2 MHz */
273    OSC_FRQRANGE_2TO9_gc = (0x01<<6),  /* 2 - 9 MHz */
274    OSC_FRQRANGE_9TO12_gc = (0x02<<6),  /* 9 - 12 MHz */
275    OSC_FRQRANGE_12TO16_gc = (0x03<<6),  /* 12 - 16 MHz */
276} OSC_FRQRANGE_t;
277
278/* External Oscillator Selection and Startup Time */
279typedef enum OSC_XOSCSEL_enum
280{
281    OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),  /* External Clock - 6 CLK */
282    OSC_XOSCSEL_32KHz_gc = (0x02<<0),  /* 32kHz TOSC - 32K CLK */
283    OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),  /* 0.4-16MHz XTAL - 256 CLK */
284    OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),  /* 0.4-16MHz XTAL - 1K CLK */
285    OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),  /* 0.4-16MHz XTAL - 16K CLK */
286} OSC_XOSCSEL_t;
287
288/* PLL Clock Source */
289typedef enum OSC_PLLSRC_enum
290{
291    OSC_PLLSRC_RC2M_gc = (0x00<<6),  /* Internal 2MHz RC Oscillator */
292    OSC_PLLSRC_RC32M_gc = (0x02<<6),  /* Internal 32MHz RC Oscillator */
293    OSC_PLLSRC_XOSC_gc = (0x03<<6),  /* External Oscillator */
294} OSC_PLLSRC_t;
295
296
297/*
298--------------------------------------------------------------------------
299DFLL - DFLL
300--------------------------------------------------------------------------
301*/
302
303/* DFLL */
304typedef struct DFLL_struct
305{
306    register8_t CTRL;  /* Control Register */
307    register8_t reserved_0x01;
308    register8_t CALA;  /* Calibration Register A */
309    register8_t CALB;  /* Calibration Register B */
310    register8_t COMP0;  /* Oscillator Compare Register 0 */
311    register8_t COMP1;  /* Oscillator Compare Register 1 */
312    register8_t COMP2;  /* Oscillator Compare Register 2 */
313    register8_t reserved_0x07;
314} DFLL_t;
315
316
317/*
318--------------------------------------------------------------------------
319RST - Reset
320--------------------------------------------------------------------------
321*/
322
323/* Reset */
324typedef struct RST_struct
325{
326    register8_t STATUS;  /* Status Register */
327    register8_t CTRL;  /* Control Register */
328} RST_t;
329
330
331/*
332--------------------------------------------------------------------------
333WDT - Watch-Dog Timer
334--------------------------------------------------------------------------
335*/
336
337/* Watch-Dog Timer */
338typedef struct WDT_struct
339{
340    register8_t CTRL;  /* Control */
341    register8_t WINCTRL;  /* Windowed Mode Control */
342    register8_t STATUS;  /* Status */
343} WDT_t;
344
345/* Period setting */
346typedef enum WDT_PER_enum
347{
348    WDT_PER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
349    WDT_PER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
350    WDT_PER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
351    WDT_PER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
352    WDT_PER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
353    WDT_PER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
354    WDT_PER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
355    WDT_PER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
356    WDT_PER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
357    WDT_PER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
358    WDT_PER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
359} WDT_PER_t;
360
361/* Closed window period */
362typedef enum WDT_WPER_enum
363{
364    WDT_WPER_8CLK_gc = (0x00<<2),  /* 8 cycles (8ms @ 3.3V) */
365    WDT_WPER_16CLK_gc = (0x01<<2),  /* 16 cycles (16ms @ 3.3V) */
366    WDT_WPER_32CLK_gc = (0x02<<2),  /* 32 cycles (32ms @ 3.3V) */
367    WDT_WPER_64CLK_gc = (0x03<<2),  /* 64 cycles (64ms @ 3.3V) */
368    WDT_WPER_128CLK_gc = (0x04<<2),  /* 128 cycles (0.125s @ 3.3V) */
369    WDT_WPER_256CLK_gc = (0x05<<2),  /* 256 cycles (0.25s @ 3.3V) */
370    WDT_WPER_512CLK_gc = (0x06<<2),  /* 512 cycles (0.5s @ 3.3V) */
371    WDT_WPER_1KCLK_gc = (0x07<<2),  /* 1K cycles (1s @ 3.3V) */
372    WDT_WPER_2KCLK_gc = (0x08<<2),  /* 2K cycles (2s @ 3.3V) */
373    WDT_WPER_4KCLK_gc = (0x09<<2),  /* 4K cycles (4s @ 3.3V) */
374    WDT_WPER_8KCLK_gc = (0x0A<<2),  /* 8K cycles (8s @ 3.3V) */
375} WDT_WPER_t;
376
377
378/*
379--------------------------------------------------------------------------
380MCU - MCU Control
381--------------------------------------------------------------------------
382*/
383
384/* MCU Control */
385typedef struct MCU_struct
386{
387    register8_t DEVID0;  /* Device ID byte 0 */
388    register8_t DEVID1;  /* Device ID byte 1 */
389    register8_t DEVID2;  /* Device ID byte 2 */
390    register8_t REVID;  /* Revision ID */
391    register8_t JTAGUID;  /* JTAG User ID */
392    register8_t reserved_0x05;
393    register8_t MCUCR;  /* MCU Control */
394    register8_t reserved_0x07;
395    register8_t EVSYSLOCK;  /* Event System Lock */
396    register8_t AWEXLOCK;  /* AWEX Lock */
397    register8_t reserved_0x0A;
398    register8_t reserved_0x0B;
399} MCU_t;
400
401
402/*
403--------------------------------------------------------------------------
404PMIC - Programmable Multi-level Interrupt Controller
405--------------------------------------------------------------------------
406*/
407
408/* Programmable Multi-level Interrupt Controller */
409typedef struct PMIC_struct
410{
411    register8_t STATUS;  /* Status Register */
412    register8_t INTPRI;  /* Interrupt Priority */
413    register8_t CTRL;  /* Control Register */
414} PMIC_t;
415
416
417
418/*
419--------------------------------------------------------------------------
420CRC - Cyclic Redundancy Checker
421--------------------------------------------------------------------------
422*/
423
424/* Cyclic Redundancy Checker */
425typedef struct CRC_struct
426{
427    register8_t CTRL;  /* Control Register */
428    register8_t STATUS;  /* Status Register */
429    register8_t reserved_0x02;
430    register8_t DATAIN;  /* Data Input */
431    register8_t CHECKSUM0;  /* Checksum byte 0 */
432    register8_t CHECKSUM1;  /* Checksum byte 1 */
433    register8_t CHECKSUM2;  /* Checksum byte 2 */
434    register8_t CHECKSUM3;  /* Checksum byte 3 */
435} CRC_t;
436
437/* Reset */
438typedef enum CRC_RESET_enum
439{
440    CRC_RESET_NO_gc = (0x00<<6),  /* No Reset */
441    CRC_RESET_RESET0_gc = (0x02<<6),  /* Reset CRC with CHECKSUM to all zeros */
442    CRC_RESET_RESET1_gc = (0x03<<6),  /* Reset CRC with CHECKSUM to all ones */
443} CRC_RESET_t;
444
445/* Input Source */
446typedef enum CRC_SOURCE_enum
447{
448    CRC_SOURCE_DISABLE_gc = (0x00<<0),  /* Disabled */
449    CRC_SOURCE_IO_gc = (0x01<<0),  /* I/O Interface */
450    CRC_SOURCE_FLASH_gc = (0x02<<0),  /* Flash */
451} CRC_SOURCE_t;
452
453
454/*
455--------------------------------------------------------------------------
456EVSYS - Event System
457--------------------------------------------------------------------------
458*/
459
460/* Event System */
461typedef struct EVSYS_struct
462{
463    register8_t CH0MUX;  /* Event Channel 0 Multiplexer */
464    register8_t CH1MUX;  /* Event Channel 1 Multiplexer */
465    register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
466    register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
467    register8_t reserved_0x04;
468    register8_t reserved_0x05;
469    register8_t reserved_0x06;
470    register8_t reserved_0x07;
471    register8_t CH0CTRL;  /* Channel 0 Control Register */
472    register8_t CH1CTRL;  /* Channel 1 Control Register */
473    register8_t CH2CTRL;  /* Channel 2 Control Register */
474    register8_t CH3CTRL;  /* Channel 3 Control Register */
475    register8_t reserved_0x0C;
476    register8_t reserved_0x0D;
477    register8_t reserved_0x0E;
478    register8_t reserved_0x0F;
479    register8_t STROBE;  /* Event Strobe */
480    register8_t DATA;  /* Event Data */
481} EVSYS_t;
482
483/* Quadrature Decoder Index Recognition Mode */
484typedef enum EVSYS_QDIRM_enum
485{
486    EVSYS_QDIRM_00_gc = (0x00<<5),  /* QDPH0 = 0, QDPH90 = 0 */
487    EVSYS_QDIRM_01_gc = (0x01<<5),  /* QDPH0 = 0, QDPH90 = 1 */
488    EVSYS_QDIRM_10_gc = (0x02<<5),  /* QDPH0 = 1, QDPH90 = 0 */
489    EVSYS_QDIRM_11_gc = (0x03<<5),  /* QDPH0 = 1, QDPH90 = 1 */
490} EVSYS_QDIRM_t;
491
492/* Digital filter coefficient */
493typedef enum EVSYS_DIGFILT_enum
494{
495    EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),  /* 1 SAMPLE */
496    EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),  /* 2 SAMPLES */
497    EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),  /* 3 SAMPLES */
498    EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),  /* 4 SAMPLES */
499    EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),  /* 5 SAMPLES */
500    EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),  /* 6 SAMPLES */
501    EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),  /* 7 SAMPLES */
502    EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),  /* 8 SAMPLES */
503} EVSYS_DIGFILT_t;
504
505/* Event Channel multiplexer input selection */
506typedef enum EVSYS_CHMUX_enum
507{
508    EVSYS_CHMUX_OFF_gc = (0x00<<0),  /* Off */
509    EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),  /* RTC Overflow */
510    EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),  /* RTC Compare Match */
511    EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),  /* Analog Comparator A Channel 0 */
512    EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),  /* Analog Comparator A Channel 1 */
513    EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),  /* Analog Comparator A Window */
514    EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),  /* ADC A Channel 0 */
515    EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),  /* Port A, Pin0 */
516    EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),  /* Port A, Pin1 */
517    EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),  /* Port A, Pin2 */
518    EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),  /* Port A, Pin3 */
519    EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),  /* Port A, Pin4 */
520    EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),  /* Port A, Pin5 */
521    EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),  /* Port A, Pin6 */
522    EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),  /* Port A, Pin7 */
523    EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),  /* Port B, Pin0 */
524    EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),  /* Port B, Pin1 */
525    EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),  /* Port B, Pin2 */
526    EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),  /* Port B, Pin3 */
527    EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),  /* Port B, Pin4 */
528    EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),  /* Port B, Pin5 */
529    EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),  /* Port B, Pin6 */
530    EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),  /* Port B, Pin7 */
531    EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),  /* Port C, Pin0 */
532    EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),  /* Port C, Pin1 */
533    EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),  /* Port C, Pin2 */
534    EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),  /* Port C, Pin3 */
535    EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),  /* Port C, Pin4 */
536    EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),  /* Port C, Pin5 */
537    EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),  /* Port C, Pin6 */
538    EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),  /* Port C, Pin7 */
539    EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),  /* Port D, Pin0 */
540    EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),  /* Port D, Pin1 */
541    EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),  /* Port D, Pin2 */
542    EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),  /* Port D, Pin3 */
543    EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),  /* Port D, Pin4 */
544    EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),  /* Port D, Pin5 */
545    EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),  /* Port D, Pin6 */
546    EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),  /* Port D, Pin7 */
547    EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),  /* Port E, Pin0 */
548    EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),  /* Port E, Pin1 */
549    EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),  /* Port E, Pin2 */
550    EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),  /* Port E, Pin3 */
551    EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),  /* Port E, Pin4 */
552    EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),  /* Port E, Pin5 */
553    EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),  /* Port E, Pin6 */
554    EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),  /* Port E, Pin7 */
555    EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),  /* Port F, Pin0 */
556    EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),  /* Port F, Pin1 */
557    EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),  /* Port F, Pin2 */
558    EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),  /* Port F, Pin3 */
559    EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),  /* Port F, Pin4 */
560    EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),  /* Port F, Pin5 */
561    EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),  /* Port F, Pin6 */
562    EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),  /* Port F, Pin7 */
563    EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),  /* Prescaler, divide by 1 */
564    EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),  /* Prescaler, divide by 2 */
565    EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),  /* Prescaler, divide by 4 */
566    EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),  /* Prescaler, divide by 8 */
567    EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),  /* Prescaler, divide by 16 */
568    EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),  /* Prescaler, divide by 32 */
569    EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),  /* Prescaler, divide by 64 */
570    EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
571    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
572    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
573    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
574    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
575    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
576    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
577    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
578    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
579    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
580    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
581    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
582    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
583    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
584    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
585    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
586    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
587    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
588    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
589    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
590    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
591    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
592    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
593    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
594    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
595    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
596    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
597    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
598    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
599    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
600    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
601    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
602    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
603    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
604    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
605    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
606    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
607    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
608    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
609    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
610    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
611    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
612    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
613    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
614    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
615    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
616    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
617    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
618    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
619} EVSYS_CHMUX_t;
620
621
622/*
623--------------------------------------------------------------------------
624NVM - Non Volatile Memory Controller
625--------------------------------------------------------------------------
626*/
627
628/* Non-volatile Memory Controller */
629typedef struct NVM_struct
630{
631    register8_t ADDR0;  /* Address Register 0 */
632    register8_t ADDR1;  /* Address Register 1 */
633    register8_t ADDR2;  /* Address Register 2 */
634    register8_t reserved_0x03;
635    register8_t DATA0;  /* Data Register 0 */
636    register8_t DATA1;  /* Data Register 1 */
637    register8_t DATA2;  /* Data Register 2 */
638    register8_t reserved_0x07;
639    register8_t reserved_0x08;
640    register8_t reserved_0x09;
641    register8_t CMD;  /* Command */
642    register8_t CTRLA;  /* Control Register A */
643    register8_t CTRLB;  /* Control Register B */
644    register8_t INTCTRL;  /* Interrupt Control */
645    register8_t reserved_0x0E;
646    register8_t STATUS;  /* Status */
647    register8_t LOCKBITS;  /* Lock Bits */
648} NVM_t;
649
650/*
651--------------------------------------------------------------------------
652NVM - Non Volatile Memory Controller
653--------------------------------------------------------------------------
654*/
655
656/* Lock Bits */
657typedef struct NVM_LOCKBITS_struct
658{
659    register8_t LOCKBITS;  /* Lock Bits */
660} NVM_LOCKBITS_t;
661
662/*
663--------------------------------------------------------------------------
664NVM - Non Volatile Memory Controller
665--------------------------------------------------------------------------
666*/
667
668/* Fuses */
669typedef struct NVM_FUSES_struct
670{
671    register8_t FUSEBYTE0;  /* User ID */
672    register8_t FUSEBYTE1;  /* Watchdog Configuration */
673    register8_t FUSEBYTE2;  /* Reset Configuration */
674    register8_t reserved_0x03;
675    register8_t FUSEBYTE4;  /* Start-up Configuration */
676    register8_t FUSEBYTE5;  /* EESAVE and BOD Level */
677} NVM_FUSES_t;
678
679/*
680--------------------------------------------------------------------------
681NVM - Non Volatile Memory Controller
682--------------------------------------------------------------------------
683*/
684
685/* Production Signatures */
686typedef struct NVM_PROD_SIGNATURES_struct
687{
688    register8_t RCOSC2M;  /* RCOSC 2MHz Calibration Value */
689    register8_t reserved_0x01;
690    register8_t RCOSC32K;  /* RCOSC 32kHz Calibration Value */
691    register8_t RCOSC32M;  /* RCOSC 32MHz Calibration Value */
692    register8_t reserved_0x04;
693    register8_t reserved_0x05;
694    register8_t reserved_0x06;
695    register8_t reserved_0x07;
696    register8_t LOTNUM0;  /* Lot Number Byte 0, ASCII */
697    register8_t LOTNUM1;  /* Lot Number Byte 1, ASCII */
698    register8_t LOTNUM2;  /* Lot Number Byte 2, ASCII */
699    register8_t LOTNUM3;  /* Lot Number Byte 3, ASCII */
700    register8_t LOTNUM4;  /* Lot Number Byte 4, ASCII */
701    register8_t LOTNUM5;  /* Lot Number Byte 5, ASCII */
702    register8_t reserved_0x0E;
703    register8_t reserved_0x0F;
704    register8_t WAFNUM;  /* Wafer Number */
705    register8_t reserved_0x11;
706    register8_t COORDX0;  /* Wafer Coordinate X Byte 0 */
707    register8_t COORDX1;  /* Wafer Coordinate X Byte 1 */
708    register8_t COORDY0;  /* Wafer Coordinate Y Byte 0 */
709    register8_t COORDY1;  /* Wafer Coordinate Y Byte 1 */
710    register8_t reserved_0x16;
711    register8_t reserved_0x17;
712    register8_t reserved_0x18;
713    register8_t reserved_0x19;
714    register8_t reserved_0x1A;
715    register8_t reserved_0x1B;
716    register8_t reserved_0x1C;
717    register8_t reserved_0x1D;
718    register8_t reserved_0x1E;
719    register8_t reserved_0x1F;
720    register8_t ADCACAL0;  /* ADCA Calibration Byte 0 */
721    register8_t ADCACAL1;  /* ADCA Calibration Byte 1 */
722    register8_t reserved_0x22;
723    register8_t reserved_0x23;
724    register8_t ADCBCAL0;  /* ADCB Calibration Byte 0 */
725    register8_t ADCBCAL1;  /* ADCB Calibration Byte 1 */
726    register8_t reserved_0x26;
727    register8_t reserved_0x27;
728    register8_t reserved_0x28;
729    register8_t reserved_0x29;
730    register8_t reserved_0x2A;
731    register8_t reserved_0x2B;
732    register8_t reserved_0x2C;
733    register8_t reserved_0x2D;
734    register8_t TEMPSENSE0;  /* Temperature Sensor Calibration Byte 0 */
735    register8_t TEMPSENSE1;  /* Temperature Sensor Calibration Byte 0 */
736    register8_t DACAOFFCAL;  /* DACA Calibration Byte 0 */
737    register8_t DACAGAINCAL;  /* DACA Calibration Byte 1 */
738    register8_t DACBOFFCAL;  /* DACB Calibration Byte 0 */
739    register8_t DACBGAINCAL;  /* DACB Calibration Byte 1 */
740    register8_t reserved_0x34;
741    register8_t reserved_0x35;
742    register8_t reserved_0x36;
743    register8_t reserved_0x37;
744    register8_t reserved_0x38;
745    register8_t reserved_0x39;
746    register8_t reserved_0x3A;
747    register8_t reserved_0x3B;
748    register8_t reserved_0x3C;
749    register8_t reserved_0x3D;
750    register8_t reserved_0x3E;
751} NVM_PROD_SIGNATURES_t;
752
753/* NVM Command */
754typedef enum NVM_CMD_enum
755{
756    NVM_CMD_NO_OPERATION_gc = (0x00<<0),  /* Noop/Ordinary LPM */
757    NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),  /* Read calibration row */
758    NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),  /* Read user signature row */
759    NVM_CMD_READ_EEPROM_gc = (0x06<<0),  /* Read EEPROM */
760    NVM_CMD_READ_FUSES_gc = (0x07<<0),  /* Read fuse byte */
761    NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),  /* Write lock bits */
762    NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
763    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
764    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
765    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
766    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
767    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
768    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
769    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
770    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
771    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
772    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
773    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
774    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
775    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
776    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
777    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
778    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
779    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
780    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
781    NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
782} NVM_CMD_t;
783
784/* SPM ready interrupt level */
785typedef enum NVM_SPMLVL_enum
786{
787    NVM_SPMLVL_OFF_gc = (0x00<<2),  /* Interrupt disabled */
788    NVM_SPMLVL_LO_gc = (0x01<<2),  /* Low level */
789    NVM_SPMLVL_MED_gc = (0x02<<2),  /* Medium level */
790    NVM_SPMLVL_HI_gc = (0x03<<2),  /* High level */
791} NVM_SPMLVL_t;
792
793/* EEPROM ready interrupt level */
794typedef enum NVM_EELVL_enum
795{
796    NVM_EELVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
797    NVM_EELVL_LO_gc = (0x01<<0),  /* Low level */
798    NVM_EELVL_MED_gc = (0x02<<0),  /* Medium level */
799    NVM_EELVL_HI_gc = (0x03<<0),  /* High level */
800} NVM_EELVL_t;
801
802/* Boot lock bits - boot setcion */
803typedef enum NVM_BLBB_enum
804{
805    NVM_BLBB_NOLOCK_gc = (0x03<<6),  /* No locks */
806    NVM_BLBB_WLOCK_gc = (0x02<<6),  /* Write not allowed */
807    NVM_BLBB_RLOCK_gc = (0x01<<6),  /* Read not allowed */
808    NVM_BLBB_RWLOCK_gc = (0x00<<6),  /* Read and write not allowed */
809} NVM_BLBB_t;
810
811/* Boot lock bits - application section */
812typedef enum NVM_BLBA_enum
813{
814    NVM_BLBA_NOLOCK_gc = (0x03<<4),  /* No locks */
815    NVM_BLBA_WLOCK_gc = (0x02<<4),  /* Write not allowed */
816    NVM_BLBA_RLOCK_gc = (0x01<<4),  /* Read not allowed */
817    NVM_BLBA_RWLOCK_gc = (0x00<<4),  /* Read and write not allowed */
818} NVM_BLBA_t;
819
820/* Boot lock bits - application table section */
821typedef enum NVM_BLBAT_enum
822{
823    NVM_BLBAT_NOLOCK_gc = (0x03<<2),  /* No locks */
824    NVM_BLBAT_WLOCK_gc = (0x02<<2),  /* Write not allowed */
825    NVM_BLBAT_RLOCK_gc = (0x01<<2),  /* Read not allowed */
826    NVM_BLBAT_RWLOCK_gc = (0x00<<2),  /* Read and write not allowed */
827} NVM_BLBAT_t;
828
829/* Lock bits */
830typedef enum NVM_LB_enum
831{
832    NVM_LB_NOLOCK_gc = (0x03<<0),  /* No locks */
833    NVM_LB_WLOCK_gc = (0x02<<0),  /* Write not allowed */
834    NVM_LB_RWLOCK_gc = (0x00<<0),  /* Read and write not allowed */
835} NVM_LB_t;
836
837/* Boot Loader Section Reset Vector */
838typedef enum BOOTRST_enum
839{
840    BOOTRST_BOOTLDR_gc = (0x00<<6),  /* Boot Loader Reset */
841    BOOTRST_APPLICATION_gc = (0x01<<6),  /* Application Reset */
842} BOOTRST_t;
843
844/* BOD operation */
845typedef enum BOD_enum
846{
847    BOD_INSAMPLEDMODE_gc = (0x01<<0),  /* BOD enabled in sampled mode */
848    BOD_CONTINOUSLY_gc = (0x02<<0),  /* BOD enabled continuously */
849    BOD_DISABLED_gc = (0x03<<0),  /* BOD Disabled */
850} BOD_t;
851
852/* Watchdog (Window) Timeout Period */
853typedef enum WD_enum
854{
855    WD_8CLK_gc = (0x00<<4),  /* 8 cycles (8ms @ 3.3V) */
856    WD_16CLK_gc = (0x01<<4),  /* 16 cycles (16ms @ 3.3V) */
857    WD_32CLK_gc = (0x02<<4),  /* 32 cycles (32ms @ 3.3V) */
858    WD_64CLK_gc = (0x03<<4),  /* 64 cycles (64ms @ 3.3V) */
859    WD_128CLK_gc = (0x04<<4),  /* 128 cycles (0.125s @ 3.3V) */
860    WD_256CLK_gc = (0x05<<4),  /* 256 cycles (0.25s @ 3.3V) */
861    WD_512CLK_gc = (0x06<<4),  /* 512 cycles (0.5s @ 3.3V) */
862    WD_1KCLK_gc = (0x07<<4),  /* 1K cycles (1s @ 3.3V) */
863    WD_2KCLK_gc = (0x08<<4),  /* 2K cycles (2s @ 3.3V) */
864    WD_4KCLK_gc = (0x09<<4),  /* 4K cycles (4s @ 3.3V) */
865    WD_8KCLK_gc = (0x0A<<4),  /* 8K cycles (8s @ 3.3V) */
866} WD_t;
867
868/* Start-up Time */
869typedef enum SUT_enum
870{
871    SUT_0MS_gc = (0x03<<2),  /* 0 ms */
872    SUT_4MS_gc = (0x01<<2),  /* 4 ms */
873    SUT_64MS_gc = (0x00<<2),  /* 64 ms */
874} SUT_t;
875
876/* Brown Out Detection Voltage Level */
877typedef enum BODLVL_enum
878{
879    BODLVL_1V6_gc = (0x07<<0),  /* 1.6 V */
880    BODLVL_1V9_gc = (0x06<<0),  /* 1.8 V */
881    BODLVL_2V1_gc = (0x05<<0),  /* 2.0 V */
882    BODLVL_2V4_gc = (0x04<<0),  /* 2.2 V */
883    BODLVL_2V6_gc = (0x03<<0),  /* 2.4 V */
884    BODLVL_2V9_gc = (0x02<<0),  /* 2.7 V */
885    BODLVL_3V2_gc = (0x01<<0),  /* 2.9 V */
886} BODLVL_t;
887
888
889/*
890--------------------------------------------------------------------------
891AC - Analog Comparator
892--------------------------------------------------------------------------
893*/
894
895/* Analog Comparator */
896typedef struct AC_struct
897{
898    register8_t AC0CTRL;  /* Comparator 0 Control */
899    register8_t AC1CTRL;  /* Comparator 1 Control */
900    register8_t AC0MUXCTRL;  /* Comparator 0 MUX Control */
901    register8_t AC1MUXCTRL;  /* Comparator 1 MUX Control */
902    register8_t CTRLA;  /* Control Register A */
903    register8_t CTRLB;  /* Control Register B */
904    register8_t WINCTRL;  /* Window Mode Control */
905    register8_t STATUS;  /* Status */
906} AC_t;
907
908/* Interrupt mode */
909typedef enum AC_INTMODE_enum
910{
911    AC_INTMODE_BOTHEDGES_gc = (0x00<<6),  /* Interrupt on both edges */
912    AC_INTMODE_FALLING_gc = (0x02<<6),  /* Interrupt on falling edge */
913    AC_INTMODE_RISING_gc = (0x03<<6),  /* Interrupt on rising edge */
914} AC_INTMODE_t;
915
916/* Interrupt level */
917typedef enum AC_INTLVL_enum
918{
919    AC_INTLVL_OFF_gc = (0x00<<4),  /* Interrupt disabled */
920    AC_INTLVL_LO_gc = (0x01<<4),  /* Low level */
921    AC_INTLVL_MED_gc = (0x02<<4),  /* Medium level */
922    AC_INTLVL_HI_gc = (0x03<<4),  /* High level */
923} AC_INTLVL_t;
924
925/* Hysteresis mode selection */
926typedef enum AC_HYSMODE_enum
927{
928    AC_HYSMODE_NO_gc = (0x00<<1),  /* No hysteresis */
929    AC_HYSMODE_SMALL_gc = (0x01<<1),  /* Small hysteresis */
930    AC_HYSMODE_LARGE_gc = (0x02<<1),  /* Large hysteresis */
931} AC_HYSMODE_t;
932
933/* Positive input multiplexer selection */
934typedef enum AC_MUXPOS_enum
935{
936    AC_MUXPOS_PIN0_gc = (0x00<<3),  /* Pin 0 */
937    AC_MUXPOS_PIN1_gc = (0x01<<3),  /* Pin 1 */
938    AC_MUXPOS_PIN2_gc = (0x02<<3),  /* Pin 2 */
939    AC_MUXPOS_PIN3_gc = (0x03<<3),  /* Pin 3 */
940    AC_MUXPOS_PIN4_gc = (0x04<<3),  /* Pin 4 */
941    AC_MUXPOS_PIN5_gc = (0x05<<3),  /* Pin 5 */
942    AC_MUXPOS_PIN6_gc = (0x06<<3),  /* Pin 6 */
943    AC_MUXPOS_DAC_gc = (0x07<<3),  /* DAC output */
944} AC_MUXPOS_t;
945
946/* Negative input multiplexer selection */
947typedef enum AC_MUXNEG_enum
948{
949    AC_MUXNEG_PIN0_gc = (0x00<<0),  /* Pin 0 */
950    AC_MUXNEG_PIN1_gc = (0x01<<0),  /* Pin 1 */
951    AC_MUXNEG_PIN3_gc = (0x02<<0),  /* Pin 3 */
952    AC_MUXNEG_PIN5_gc = (0x03<<0),  /* Pin 5 */
953    AC_MUXNEG_PIN7_gc = (0x04<<0),  /* Pin 7 */
954    AC_MUXNEG_DAC_gc = (0x05<<0),  /* DAC output */
955    AC_MUXNEG_BANDGAP_gc = (0x06<<0),  /* Bandgap Reference */
956    AC_MUXNEG_SCALER_gc = (0x07<<0),  /* Internal voltage scaler */
957} AC_MUXNEG_t;
958
959/* Windows interrupt mode */
960typedef enum AC_WINTMODE_enum
961{
962    AC_WINTMODE_ABOVE_gc = (0x00<<2),  /* Interrupt on above window */
963    AC_WINTMODE_INSIDE_gc = (0x01<<2),  /* Interrupt on inside window */
964    AC_WINTMODE_BELOW_gc = (0x02<<2),  /* Interrupt on below window */
965    AC_WINTMODE_OUTSIDE_gc = (0x03<<2),  /* Interrupt on outside window */
966} AC_WINTMODE_t;
967
968/* Window interrupt level */
969typedef enum AC_WINTLVL_enum
970{
971    AC_WINTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
972    AC_WINTLVL_LO_gc = (0x01<<0),  /* Low priority */
973    AC_WINTLVL_MED_gc = (0x02<<0),  /* Medium priority */
974    AC_WINTLVL_HI_gc = (0x03<<0),  /* High priority */
975} AC_WINTLVL_t;
976
977/* Window mode state */
978typedef enum AC_WSTATE_enum
979{
980    AC_WSTATE_ABOVE_gc = (0x00<<6),  /* Signal above window */
981    AC_WSTATE_INSIDE_gc = (0x01<<6),  /* Signal inside window */
982    AC_WSTATE_BELOW_gc = (0x02<<6),  /* Signal below window */
983} AC_WSTATE_t;
984
985
986/*
987--------------------------------------------------------------------------
988ADC - Analog/Digital Converter
989--------------------------------------------------------------------------
990*/
991
992/* ADC Channel */
993typedef struct ADC_CH_struct
994{
995    register8_t CTRL;  /* Control Register */
996    register8_t MUXCTRL;  /* MUX Control */
997    register8_t INTCTRL;  /* Channel Interrupt Control */
998    register8_t INTFLAGS;  /* Interrupt Flags */
999    _WORDREGISTER(RES);  /* Channel Result */
1000    register8_t reserved_0x6;
1001    register8_t reserved_0x7;
1002} ADC_CH_t;
1003
1004/*
1005--------------------------------------------------------------------------
1006ADC - Analog/Digital Converter
1007--------------------------------------------------------------------------
1008*/
1009
1010/* Analog-to-Digital Converter */
1011typedef struct ADC_struct
1012{
1013    register8_t CTRLA;  /* Control Register A */
1014    register8_t CTRLB;  /* Control Register B */
1015    register8_t REFCTRL;  /* Reference Control */
1016    register8_t EVCTRL;  /* Event Control */
1017    register8_t PRESCALER;  /* Clock Prescaler */
1018    register8_t reserved_0x05;
1019    register8_t INTFLAGS;  /* Interrupt Flags */
1020    register8_t reserved_0x07;
1021    register8_t reserved_0x08;
1022    register8_t reserved_0x09;
1023    register8_t reserved_0x0A;
1024    register8_t reserved_0x0B;
1025    _WORDREGISTER(CAL);  /* Calibration Value */
1026    register8_t reserved_0x0E;
1027    register8_t reserved_0x0F;
1028    _WORDREGISTER(CH0RES);  /* Channel 0 Result */
1029    register8_t reserved_0x12;
1030    register8_t reserved_0x13;
1031    register8_t reserved_0x14;
1032    register8_t reserved_0x15;
1033    register8_t reserved_0x16;
1034    register8_t reserved_0x17;
1035    _WORDREGISTER(CMP);  /* Compare Value */
1036    register8_t reserved_0x1A;
1037    register8_t reserved_0x1B;
1038    register8_t reserved_0x1C;
1039    register8_t reserved_0x1D;
1040    register8_t reserved_0x1E;
1041    register8_t reserved_0x1F;
1042    ADC_CH_t CH0;  /* ADC Channel 0 */
1043} ADC_t;
1044
1045/* Positive input multiplexer selection */
1046typedef enum ADC_CH_MUXPOS_enum
1047{
1048    ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),  /* Input pin 0 */
1049    ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),  /* Input pin 1 */
1050    ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),  /* Input pin 2 */
1051    ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),  /* Input pin 3 */
1052    ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),  /* Input pin 4 */
1053    ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),  /* Input pin 5 */
1054    ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),  /* Input pin 6 */
1055    ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),  /* Input pin 7 */
1056} ADC_CH_MUXPOS_t;
1057
1058/* Internal input multiplexer selections */
1059typedef enum ADC_CH_MUXINT_enum
1060{
1061    ADC_CH_MUXINT_TEMP_gc = (0x00<<3),  /* Temperature Reference */
1062    ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),  /* Bandgap Reference */
1063    ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),  /* 1/10 scaled VCC */
1064    ADC_CH_MUXINT_DAC_gc = (0x03<<3),  /* DAC output */
1065} ADC_CH_MUXINT_t;
1066
1067/* Negative input multiplexer selection */
1068typedef enum ADC_CH_MUXNEG_enum
1069{
1070    ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),  /* Input pin 0 */
1071    ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),  /* Input pin 1 */
1072    ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),  /* Input pin 2 */
1073    ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),  /* Input pin 3 */
1074    ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),  /* Input pin 4 */
1075    ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),  /* Input pin 5 */
1076    ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),  /* Input pin 6 */
1077    ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),  /* Input pin 7 */
1078} ADC_CH_MUXNEG_t;
1079
1080/* Input mode */
1081typedef enum ADC_CH_INPUTMODE_enum
1082{
1083    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
1084    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
1085    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
1086    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
1087} ADC_CH_INPUTMODE_t;
1088
1089/* Gain factor */
1090typedef enum ADC_CH_GAIN_enum
1091{
1092    ADC_CH_GAIN_1X_gc = (0x00<<2),  /* 1x gain */
1093    ADC_CH_GAIN_2X_gc = (0x01<<2),  /* 2x gain */
1094    ADC_CH_GAIN_4X_gc = (0x02<<2),  /* 4x gain */
1095    ADC_CH_GAIN_8X_gc = (0x03<<2),  /* 8x gain */
1096    ADC_CH_GAIN_16X_gc = (0x04<<2),  /* 16x gain */
1097    ADC_CH_GAIN_32X_gc = (0x05<<2),  /* 32x gain */
1098    ADC_CH_GAIN_64X_gc = (0x06<<2),  /* 64x gain */
1099    ADC_CH_GAIN_DIV2_gc = (0x07<<2),  /* x/2 gain */           
1100} ADC_CH_GAIN_t;
1101
1102/* Conversion result resolution */
1103typedef enum ADC_RESOLUTION_enum
1104{
1105    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
1106    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
1107    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
1108} ADC_RESOLUTION_t;
1109
1110typedef enum ADC_CURRLIMIT_enum
1111{
1112    ADC_CURRLIMIT_NO_gc = (0x00<<5),  /* No limit */
1113    ADC_CURRLIMIT_LOW_gc = (0x01<<5),  /* Low current limit, max. sampling rate 1.5MSPS */
1114    ADC_CURRLIMIT_MED_gc = (0x02<<5),  /* Medium current limit, max. sampling rate 1MSPS */
1115    ADC_CURRLIMIT_HIGH_gc = (0x03<<5),  /* High current limit, max. sampling rate 0.5MSPS */
1116} ADC_CURRLIMIT_t;
1117
1118/* Voltage reference selection */
1119typedef enum ADC_REFSEL_enum
1120{
1121    ADC_REFSEL_INT1V_gc = (0x00<<4),  /* Internal 1V */
1122    ADC_REFSEL_VCC_gc = (0x01<<4),  /* Internal VCC/1.6V */
1123    ADC_REFSEL_AREFA_gc = (0x02<<4),  /* External reference on PORT A */
1124    ADC_REFSEL_AREFB_gc = (0x03<<4),  /* External reference on PORT B */
1125} ADC_REFSEL_t;
1126
1127/* Channel sweep selection */
1128typedef enum ADC_SWEEP_enum
1129{
1130    ADC_SWEEP_0_gc = (0x00<<6),  /* ADC Channel 0 */
1131} ADC_SWEEP_t;
1132
1133/* Event channel input selection */
1134typedef enum ADC_EVSEL_enum
1135{
1136    ADC_EVSEL_0123_gc = (0x00<<3),  /* Event Channel 0,1,2,3 */
1137    ADC_EVSEL_1234_gc = (0x01<<3),  /* Event Channel 1,2,3,4 */
1138    ADC_EVSEL_2345_gc = (0x02<<3),  /* Event Channel 2,3,4,5 */
1139    ADC_EVSEL_3456_gc = (0x03<<3),  /* Event Channel 3,4,5,6 */
1140    ADC_EVSEL_4567_gc = (0x04<<3),  /* Event Channel 4,5,6,7 */
1141    ADC_EVSEL_567_gc = (0x05<<3),  /* Event Channel 5,6,7 */
1142    ADC_EVSEL_67_gc = (0x06<<3),  /* Event Channel 6,7 */
1143    ADC_EVSEL_7_gc = (0x07<<3),  /* Event Channel 7 */
1144} ADC_EVSEL_t;
1145
1146/* Event action selection */
1147typedef enum ADC_EVACT_enum
1148{
1149    ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
1150    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
1151} ADC_EVACT_t;
1152
1153/* Interupt mode */
1154typedef enum ADC_CH_INTMODE_enum
1155{
1156    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
1157    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
1158    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
1159} ADC_CH_INTMODE_t;
1160
1161/* Interrupt level */
1162typedef enum ADC_CH_INTLVL_enum
1163{
1164    ADC_CH_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt disabled */
1165    ADC_CH_INTLVL_LO_gc = (0x01<<0),  /* Low level */
1166    ADC_CH_INTLVL_MED_gc = (0x02<<0),  /* Medium level */
1167    ADC_CH_INTLVL_HI_gc = (0x03<<0),  /* High level */
1168} ADC_CH_INTLVL_t;
1169
1170/* Clock prescaler */
1171typedef enum ADC_PRESCALER_enum
1172{
1173    ADC_PRESCALER_DIV4_gc = (0x00<<0),  /* Divide clock by 4 */
1174    ADC_PRESCALER_DIV8_gc = (0x01<<0),  /* Divide clock by 8 */
1175    ADC_PRESCALER_DIV16_gc = (0x02<<0),  /* Divide clock by 16 */
1176    ADC_PRESCALER_DIV32_gc = (0x03<<0),  /* Divide clock by 32 */
1177    ADC_PRESCALER_DIV64_gc = (0x04<<0),  /* Divide clock by 64 */
1178    ADC_PRESCALER_DIV128_gc = (0x05<<0),  /* Divide clock by 128 */
1179    ADC_PRESCALER_DIV256_gc = (0x06<<0),  /* Divide clock by 256 */
1180    ADC_PRESCALER_DIV512_gc = (0x07<<0),  /* Divide clock by 512 */
1181} ADC_PRESCALER_t;
1182
1183
1184/*
1185--------------------------------------------------------------------------
1186RTC - Real-Time Clounter
1187--------------------------------------------------------------------------
1188*/
1189
1190/* Real-Time Counter */
1191typedef struct RTC_struct
1192{
1193    register8_t CTRL;  /* Control Register */
1194    register8_t STATUS;  /* Status Register */
1195    register8_t INTCTRL;  /* Interrupt Control Register */
1196    register8_t INTFLAGS;  /* Interrupt Flags */
1197    register8_t TEMP;  /* Temporary register */
1198    register8_t reserved_0x05;
1199    register8_t reserved_0x06;
1200    register8_t reserved_0x07;
1201    _WORDREGISTER(CNT);  /* Count Register */
1202    _WORDREGISTER(PER);  /* Period Register */
1203    _WORDREGISTER(COMP);  /* Compare Register */
1204} RTC_t;
1205
1206/* Prescaler Factor */
1207typedef enum RTC_PRESCALER_enum
1208{
1209    RTC_PRESCALER_OFF_gc = (0x00<<0),  /* RTC Off */
1210    RTC_PRESCALER_DIV1_gc = (0x01<<0),  /* RTC Clock */
1211    RTC_PRESCALER_DIV2_gc = (0x02<<0),  /* RTC Clock / 2 */
1212    RTC_PRESCALER_DIV8_gc = (0x03<<0),  /* RTC Clock / 8 */
1213    RTC_PRESCALER_DIV16_gc = (0x04<<0),  /* RTC Clock / 16 */
1214    RTC_PRESCALER_DIV64_gc = (0x05<<0),  /* RTC Clock / 64 */
1215    RTC_PRESCALER_DIV256_gc = (0x06<<0),  /* RTC Clock / 256 */
1216    RTC_PRESCALER_DIV1024_gc = (0x07<<0),  /* RTC Clock / 1024 */
1217} RTC_PRESCALER_t;
1218
1219/* Compare Interrupt level */
1220typedef enum RTC_COMPINTLVL_enum
1221{
1222    RTC_COMPINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1223    RTC_COMPINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1224    RTC_COMPINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1225    RTC_COMPINTLVL_HI_gc = (0x03<<2),  /* High Level */
1226} RTC_COMPINTLVL_t;
1227
1228/* Overflow Interrupt level */
1229typedef enum RTC_OVFINTLVL_enum
1230{
1231    RTC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1232    RTC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1233    RTC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1234    RTC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1235} RTC_OVFINTLVL_t;
1236
1237
1238/*
1239--------------------------------------------------------------------------
1240EBI - External Bus Interface
1241--------------------------------------------------------------------------
1242*/
1243
1244/* EBI Chip Select Module */
1245typedef struct EBI_CS_struct
1246{
1247    register8_t CTRLA;  /* Chip Select Control Register A */
1248    register8_t CTRLB;  /* Chip Select Control Register B */
1249    _WORDREGISTER(BASEADDR);  /* Chip Select Base Address */
1250} EBI_CS_t;
1251
1252/*
1253--------------------------------------------------------------------------
1254EBI - External Bus Interface
1255--------------------------------------------------------------------------
1256*/
1257
1258/* External Bus Interface */
1259typedef struct EBI_struct
1260{
1261    register8_t CTRL;  /* Control */
1262    register8_t SDRAMCTRLA;  /* SDRAM Control Register A */
1263    register8_t reserved_0x02;
1264    register8_t reserved_0x03;
1265    _WORDREGISTER(REFRESH);  /* SDRAM Refresh Period */
1266    _WORDREGISTER(INITDLY);  /* SDRAM Initialization Delay */
1267    register8_t SDRAMCTRLB;  /* SDRAM Control Register B */
1268    register8_t SDRAMCTRLC;  /* SDRAM Control Register C */
1269    register8_t reserved_0x0A;
1270    register8_t reserved_0x0B;
1271    register8_t reserved_0x0C;
1272    register8_t reserved_0x0D;
1273    register8_t reserved_0x0E;
1274    register8_t reserved_0x0F;
1275    EBI_CS_t CS0;  /* Chip Select 0 */
1276    EBI_CS_t CS1;  /* Chip Select 1 */
1277    EBI_CS_t CS2;  /* Chip Select 2 */
1278    EBI_CS_t CS3;  /* Chip Select 3 */
1279} EBI_t;
1280
1281/* Chip Select adress space */
1282typedef enum EBI_CS_ASIZE_enum
1283{
1284    EBI_CS_ASIZE_256B_gc = (0x00<<2),  /* 256 bytes */
1285    EBI_CS_ASIZE_512B_gc = (0x01<<2),  /* 512 bytes */
1286    EBI_CS_ASIZE_1KB_gc = (0x02<<2),  /* 1K bytes */
1287    EBI_CS_ASIZE_2KB_gc = (0x03<<2),  /* 2K bytes */
1288    EBI_CS_ASIZE_4KB_gc = (0x04<<2),  /* 4K bytes */
1289    EBI_CS_ASIZE_8KB_gc = (0x05<<2),  /* 8K bytes */
1290    EBI_CS_ASIZE_16KB_gc = (0x06<<2),  /* 16K bytes */
1291    EBI_CS_ASIZE_32KB_gc = (0x07<<2),  /* 32K bytes */
1292    EBI_CS_ASIZE_64KB_gc = (0x08<<2),  /* 64K bytes */
1293    EBI_CS_ASIZE_128KB_gc = (0x09<<2),  /* 128K bytes */
1294    EBI_CS_ASIZE_256KB_gc = (0x0A<<2),  /* 256K bytes */
1295    EBI_CS_ASIZE_512KB_gc = (0x0B<<2),  /* 512K bytes */
1296    EBI_CS_ASIZE_1MB_gc = (0x0C<<2),  /* 1M bytes */
1297    EBI_CS_ASIZE_2MB_gc = (0x0D<<2),  /* 2M bytes */
1298    EBI_CS_ASIZE_4MB_gc = (0x0E<<2),  /* 4M bytes */
1299    EBI_CS_ASIZE_8MB_gc = (0x0F<<2),  /* 8M bytes */
1300    EBI_CS_ASIZE_16M_gc = (0x10<<2),  /* 16M bytes */
1301} EBI_CS_ASIZE_t;
1302
1303/*  */
1304typedef enum EBI_CS_SRWS_enum
1305{
1306    EBI_CS_SRWS_0CLK_gc = (0x00<<0),  /* 0 cycles */
1307    EBI_CS_SRWS_1CLK_gc = (0x01<<0),  /* 1 cycle */
1308    EBI_CS_SRWS_2CLK_gc = (0x02<<0),  /* 2 cycles */
1309    EBI_CS_SRWS_3CLK_gc = (0x03<<0),  /* 3 cycles */
1310    EBI_CS_SRWS_4CLK_gc = (0x04<<0),  /* 4 cycles */
1311    EBI_CS_SRWS_5CLK_gc = (0x05<<0),  /* 5 cycle */
1312    EBI_CS_SRWS_6CLK_gc = (0x06<<0),  /* 6 cycles */
1313    EBI_CS_SRWS_7CLK_gc = (0x07<<0),  /* 7 cycles */
1314} EBI_CS_SRWS_t;
1315
1316/* Chip Select address mode */
1317typedef enum EBI_CS_MODE_enum
1318{
1319    EBI_CS_MODE_DISABLED_gc = (0x00<<0),  /* Chip Select Disabled */
1320    EBI_CS_MODE_SRAM_gc = (0x01<<0),  /* Chip Select in SRAM mode */
1321    EBI_CS_MODE_LPC_gc = (0x02<<0),  /* Chip Select in SRAM LPC mode */
1322    EBI_CS_MODE_SDRAM_gc = (0x03<<0),  /* Chip Select in SDRAM mode */
1323} EBI_CS_MODE_t;
1324
1325/* Chip Select SDRAM mode */
1326typedef enum EBI_CS_SDMODE_enum
1327{
1328    EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),  /* Normal mode */
1329    EBI_CS_SDMODE_LOAD_gc = (0x01<<0),  /* Load Mode Register command mode */
1330} EBI_CS_SDMODE_t;
1331
1332/*  */
1333typedef enum EBI_SDDATAW_enum
1334{
1335    EBI_SDDATAW_4BIT_gc = (0x00<<6),  /* 4-bit data bus */
1336    EBI_SDDATAW_8BIT_gc = (0x01<<6),  /* 8-bit data bus */
1337} EBI_SDDATAW_t;
1338
1339/*  */
1340typedef enum EBI_LPCMODE_enum
1341{
1342    EBI_LPCMODE_ALE1_gc = (0x00<<4),  /* Data muxed with addr byte 0 */
1343    EBI_LPCMODE_ALE12_gc = (0x02<<4),  /* Data muxed with addr byte 0 and 1 */
1344} EBI_LPCMODE_t;
1345
1346/*  */
1347typedef enum EBI_SRMODE_enum
1348{
1349    EBI_SRMODE_ALE1_gc = (0x00<<2),  /* Addr byte 0 muxed with 1 */
1350    EBI_SRMODE_ALE2_gc = (0x01<<2),  /* Addr byte 0 muxed with 2 */
1351    EBI_SRMODE_ALE12_gc = (0x02<<2),  /* Addr byte 0 muxed with 1 and 2 */
1352    EBI_SRMODE_NOALE_gc = (0x03<<2),  /* No addr muxing */
1353} EBI_SRMODE_t;
1354
1355/*  */
1356typedef enum EBI_IFMODE_enum
1357{
1358    EBI_IFMODE_DISABLED_gc = (0x00<<0),  /* EBI Disabled */
1359    EBI_IFMODE_3PORT_gc = (0x01<<0),  /* 3-port mode */
1360    EBI_IFMODE_4PORT_gc = (0x02<<0),  /* 4-port mode */
1361    EBI_IFMODE_2PORT_gc = (0x03<<0),  /* 2-port mode */
1362} EBI_IFMODE_t;
1363
1364/*  */
1365typedef enum EBI_SDCOL_enum
1366{
1367    EBI_SDCOL_8BIT_gc = (0x00<<0),  /* 8 column bits */
1368    EBI_SDCOL_9BIT_gc = (0x01<<0),  /* 9 column bits */
1369    EBI_SDCOL_10BIT_gc = (0x02<<0),  /* 10 column bits */
1370    EBI_SDCOL_11BIT_gc = (0x03<<0),  /* 11 column bits */
1371} EBI_SDCOL_t;
1372
1373/*  */
1374typedef enum EBI_MRDLY_enum
1375{
1376    EBI_MRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
1377    EBI_MRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
1378    EBI_MRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
1379    EBI_MRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
1380} EBI_MRDLY_t;
1381
1382/*  */
1383typedef enum EBI_ROWCYCDLY_enum
1384{
1385    EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
1386    EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
1387    EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
1388    EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
1389    EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
1390    EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
1391    EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
1392    EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
1393} EBI_ROWCYCDLY_t;
1394
1395/*  */
1396typedef enum EBI_RPDLY_enum
1397{
1398    EBI_RPDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
1399    EBI_RPDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
1400    EBI_RPDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
1401    EBI_RPDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
1402    EBI_RPDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
1403    EBI_RPDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
1404    EBI_RPDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
1405    EBI_RPDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
1406} EBI_RPDLY_t;
1407
1408/*  */
1409typedef enum EBI_WRDLY_enum
1410{
1411    EBI_WRDLY_0CLK_gc = (0x00<<6),  /* 0 cycles */
1412    EBI_WRDLY_1CLK_gc = (0x01<<6),  /* 1 cycle */
1413    EBI_WRDLY_2CLK_gc = (0x02<<6),  /* 2 cycles */
1414    EBI_WRDLY_3CLK_gc = (0x03<<6),  /* 3 cycles */
1415} EBI_WRDLY_t;
1416
1417/*  */
1418typedef enum EBI_ESRDLY_enum
1419{
1420    EBI_ESRDLY_0CLK_gc = (0x00<<3),  /* 0 cycles */
1421    EBI_ESRDLY_1CLK_gc = (0x01<<3),  /* 1 cycle */
1422    EBI_ESRDLY_2CLK_gc = (0x02<<3),  /* 2 cycles */
1423    EBI_ESRDLY_3CLK_gc = (0x03<<3),  /* 3 cycles */
1424    EBI_ESRDLY_4CLK_gc = (0x04<<3),  /* 4 cycles */
1425    EBI_ESRDLY_5CLK_gc = (0x05<<3),  /* 5 cycle */
1426    EBI_ESRDLY_6CLK_gc = (0x06<<3),  /* 6 cycles */
1427    EBI_ESRDLY_7CLK_gc = (0x07<<3),  /* 7 cycles */
1428} EBI_ESRDLY_t;
1429
1430/*  */
1431typedef enum EBI_ROWCOLDLY_enum
1432{
1433    EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),  /* 0 cycles */
1434    EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),  /* 1 cycle */
1435    EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),  /* 2 cycles */
1436    EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),  /* 3 cycles */
1437    EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),  /* 4 cycles */
1438    EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),  /* 5 cycle */
1439    EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),  /* 6 cycles */
1440    EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),  /* 7 cycles */
1441} EBI_ROWCOLDLY_t;
1442
1443
1444/*
1445--------------------------------------------------------------------------
1446TWI - Two-Wire Interface
1447--------------------------------------------------------------------------
1448*/
1449
1450/*  */
1451typedef struct TWI_MASTER_struct
1452{
1453    register8_t CTRLA;  /* Control Register A */
1454    register8_t CTRLB;  /* Control Register B */
1455    register8_t CTRLC;  /* Control Register C */
1456    register8_t STATUS;  /* Status Register */
1457    register8_t BAUD;  /* Baurd Rate Control Register */
1458    register8_t ADDR;  /* Address Register */
1459    register8_t DATA;  /* Data Register */
1460} TWI_MASTER_t;
1461
1462/*
1463--------------------------------------------------------------------------
1464TWI - Two-Wire Interface
1465--------------------------------------------------------------------------
1466*/
1467
1468/*  */
1469typedef struct TWI_SLAVE_struct
1470{
1471    register8_t CTRLA;  /* Control Register A */
1472    register8_t CTRLB;  /* Control Register B */
1473    register8_t STATUS;  /* Status Register */
1474    register8_t ADDR;  /* Address Register */
1475    register8_t DATA;  /* Data Register */
1476    register8_t ADDRMASK;  /* Address Mask Register */
1477} TWI_SLAVE_t;
1478
1479/*
1480--------------------------------------------------------------------------
1481TWI - Two-Wire Interface
1482--------------------------------------------------------------------------
1483*/
1484
1485/* Two-Wire Interface */
1486typedef struct TWI_struct
1487{
1488    register8_t CTRL;  /* TWI Common Control Register */
1489    TWI_MASTER_t MASTER;  /* TWI master module */
1490    TWI_SLAVE_t SLAVE;  /* TWI slave module */
1491} TWI_t;
1492
1493/* Master Interrupt Level */
1494typedef enum TWI_MASTER_INTLVL_enum
1495{
1496    TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1497    TWI_MASTER_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1498    TWI_MASTER_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1499    TWI_MASTER_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1500} TWI_MASTER_INTLVL_t;
1501
1502/* Inactive Timeout */
1503typedef enum TWI_MASTER_TIMEOUT_enum
1504{
1505    TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),  /* Bus Timeout Disabled */
1506    TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),  /* 50 Microseconds */
1507    TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),  /* 100 Microseconds */
1508    TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),  /* 200 Microseconds */
1509} TWI_MASTER_TIMEOUT_t;
1510
1511/* Master Command */
1512typedef enum TWI_MASTER_CMD_enum
1513{
1514    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1515    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
1516    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
1517    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
1518} TWI_MASTER_CMD_t;
1519
1520/* Master Bus State */
1521typedef enum TWI_MASTER_BUSSTATE_enum
1522{
1523    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
1524    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
1525    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
1526    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
1527} TWI_MASTER_BUSSTATE_t;
1528
1529/* Slave Interrupt Level */
1530typedef enum TWI_SLAVE_INTLVL_enum
1531{
1532    TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
1533    TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),  /* Low Level */
1534    TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),  /* Medium Level */
1535    TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),  /* High Level */
1536} TWI_SLAVE_INTLVL_t;
1537
1538/* Slave Command */
1539typedef enum TWI_SLAVE_CMD_enum
1540{
1541    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
1542    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
1543    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
1544} TWI_SLAVE_CMD_t;
1545
1546
1547/*
1548--------------------------------------------------------------------------
1549PORT - Port Configuration
1550--------------------------------------------------------------------------
1551*/
1552
1553/* I/O port Configuration */
1554typedef struct PORTCFG_struct
1555{
1556    register8_t MPCMASK;  /* Multi-pin Configuration Mask */
1557    register8_t reserved_0x01;
1558    register8_t VPCTRLA;  /* Virtual Port Control Register A */
1559    register8_t VPCTRLB;  /* Virtual Port Control Register B */
1560    register8_t CLKEVOUT;  /* Clock and Event Out Register */
1561} PORTCFG_t;
1562
1563/*
1564--------------------------------------------------------------------------
1565PORT - Port Configuration
1566--------------------------------------------------------------------------
1567*/
1568
1569/* Virtual Port */
1570typedef struct VPORT_struct
1571{
1572    register8_t DIR;  /* I/O Port Data Direction */
1573    register8_t OUT;  /* I/O Port Output */
1574    register8_t IN;  /* I/O Port Input */
1575    register8_t INTFLAGS;  /* Interrupt Flag Register */
1576} VPORT_t;
1577
1578/*
1579--------------------------------------------------------------------------
1580PORT - Port Configuration
1581--------------------------------------------------------------------------
1582*/
1583
1584/* I/O Ports */
1585typedef struct PORT_struct
1586{
1587    register8_t DIR;  /* I/O Port Data Direction */
1588    register8_t DIRSET;  /* I/O Port Data Direction Set */
1589    register8_t DIRCLR;  /* I/O Port Data Direction Clear */
1590    register8_t DIRTGL;  /* I/O Port Data Direction Toggle */
1591    register8_t OUT;  /* I/O Port Output */
1592    register8_t OUTSET;  /* I/O Port Output Set */
1593    register8_t OUTCLR;  /* I/O Port Output Clear */
1594    register8_t OUTTGL;  /* I/O Port Output Toggle */
1595    register8_t IN;  /* I/O port Input */
1596    register8_t INTCTRL;  /* Interrupt Control Register */
1597    register8_t INT0MASK;  /* Port Interrupt 0 Mask */
1598    register8_t INT1MASK;  /* Port Interrupt 1 Mask */
1599    register8_t INTFLAGS;  /* Interrupt Flag Register */
1600    register8_t reserved_0x0D;
1601    register8_t reserved_0x0E;
1602    register8_t reserved_0x0F;
1603    register8_t PIN0CTRL;  /* Pin 0 Control Register */
1604    register8_t PIN1CTRL;  /* Pin 1 Control Register */
1605    register8_t PIN2CTRL;  /* Pin 2 Control Register */
1606    register8_t PIN3CTRL;  /* Pin 3 Control Register */
1607    register8_t PIN4CTRL;  /* Pin 4 Control Register */
1608    register8_t PIN5CTRL;  /* Pin 5 Control Register */
1609    register8_t PIN6CTRL;  /* Pin 6 Control Register */
1610    register8_t PIN7CTRL;  /* Pin 7 Control Register */
1611} PORT_t;
1612
1613/* Virtual Port 0 Mapping */
1614typedef enum PORTCFG_VP0MAP_enum
1615{
1616    PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1617    PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1618    PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1619    PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1620    PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1621    PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1622    PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1623    PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1624    PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1625    PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1626    PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1627    PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1628    PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1629    PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1630    PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1631    PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1632} PORTCFG_VP0MAP_t;
1633
1634/* Virtual Port 1 Mapping */
1635typedef enum PORTCFG_VP1MAP_enum
1636{
1637    PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1638    PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1639    PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1640    PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1641    PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1642    PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1643    PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1644    PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1645    PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1646    PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1647    PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1648    PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1649    PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1650    PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1651    PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1652    PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1653} PORTCFG_VP1MAP_t;
1654
1655/* Virtual Port 2 Mapping */
1656typedef enum PORTCFG_VP2MAP_enum
1657{
1658    PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),  /* Mapped To PORTA */
1659    PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),  /* Mapped To PORTB */
1660    PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),  /* Mapped To PORTC */
1661    PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),  /* Mapped To PORTD */
1662    PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),  /* Mapped To PORTE */
1663    PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),  /* Mapped To PORTF */
1664    PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),  /* Mapped To PORTG */
1665    PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),  /* Mapped To PORTH */
1666    PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),  /* Mapped To PORTJ */
1667    PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),  /* Mapped To PORTK */
1668    PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),  /* Mapped To PORTL */
1669    PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),  /* Mapped To PORTM */
1670    PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),  /* Mapped To PORTN */
1671    PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),  /* Mapped To PORTP */
1672    PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),  /* Mapped To PORTQ */
1673    PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),  /* Mapped To PORTR */
1674} PORTCFG_VP2MAP_t;
1675
1676/* Virtual Port 3 Mapping */
1677typedef enum PORTCFG_VP3MAP_enum
1678{
1679    PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),  /* Mapped To PORTA */
1680    PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),  /* Mapped To PORTB */
1681    PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),  /* Mapped To PORTC */
1682    PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),  /* Mapped To PORTD */
1683    PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),  /* Mapped To PORTE */
1684    PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),  /* Mapped To PORTF */
1685    PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),  /* Mapped To PORTG */
1686    PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),  /* Mapped To PORTH */
1687    PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),  /* Mapped To PORTJ */
1688    PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),  /* Mapped To PORTK */
1689    PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),  /* Mapped To PORTL */
1690    PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),  /* Mapped To PORTM */
1691    PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),  /* Mapped To PORTN */
1692    PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),  /* Mapped To PORTP */
1693    PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),  /* Mapped To PORTQ */
1694    PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),  /* Mapped To PORTR */
1695} PORTCFG_VP3MAP_t;
1696
1697/* Clock Output Port */
1698typedef enum PORTCFG_CLKOUT_enum
1699{
1700    PORTCFG_CLKOUT_OFF_gc = (0x00<<0),  /* Clock Output Disabled */
1701    PORTCFG_CLKOUT_PC7_gc = (0x01<<0),  /* Clock Output on Port C pin 7 */
1702    PORTCFG_CLKOUT_PD7_gc = (0x02<<0),  /* Clock Output on Port D pin 7 */
1703    PORTCFG_CLKOUT_PE7_gc = (0x03<<0),  /* Clock Output on Port E pin 7 */
1704} PORTCFG_CLKOUT_t;
1705
1706/* Event Output Port */
1707typedef enum PORTCFG_EVOUT_enum
1708{
1709    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
1710    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
1711    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
1712    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
1713} PORTCFG_EVOUT_t;
1714
1715/* Port Interrupt 0 Level */
1716typedef enum PORT_INT0LVL_enum
1717{
1718    PORT_INT0LVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1719    PORT_INT0LVL_LO_gc = (0x01<<0),  /* Low Level */
1720    PORT_INT0LVL_MED_gc = (0x02<<0),  /* Medium Level */
1721    PORT_INT0LVL_HI_gc = (0x03<<0),  /* High Level */
1722} PORT_INT0LVL_t;
1723
1724/* Port Interrupt 1 Level */
1725typedef enum PORT_INT1LVL_enum
1726{
1727    PORT_INT1LVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1728    PORT_INT1LVL_LO_gc = (0x01<<2),  /* Low Level */
1729    PORT_INT1LVL_MED_gc = (0x02<<2),  /* Medium Level */
1730    PORT_INT1LVL_HI_gc = (0x03<<2),  /* High Level */
1731} PORT_INT1LVL_t;
1732
1733/* Output/Pull Configuration */
1734typedef enum PORT_OPC_enum
1735{
1736    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
1737    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
1738    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
1739    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
1740    PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
1741    PORT_OPC_WIREDAND_gc = (0x05<<3),  /* Wired AND */
1742    PORT_OPC_WIREDORPULL_gc = (0x06<<3),  /* Wired OR w/ Pull-down */
1743    PORT_OPC_WIREDANDPULL_gc = (0x07<<3),  /* Wired AND w/ Pull-up */
1744} PORT_OPC_t;
1745
1746/* Input/Sense Configuration */
1747typedef enum PORT_ISC_enum
1748{
1749    PORT_ISC_BOTHEDGES_gc = (0x00<<0),  /* Sense Both Edges */
1750    PORT_ISC_RISING_gc = (0x01<<0),  /* Sense Rising Edge */
1751    PORT_ISC_FALLING_gc = (0x02<<0),  /* Sense Falling Edge */
1752    PORT_ISC_LEVEL_gc = (0x03<<0),  /* Sense Level (Transparent For Events) */
1753    PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),  /* Disable Digital Input Buffer */
1754} PORT_ISC_t;
1755
1756
1757/*
1758--------------------------------------------------------------------------
1759TC - 16-bit Timer/Counter With PWM
1760--------------------------------------------------------------------------
1761*/
1762
1763/* 16-bit Timer/Counter 0 */
1764typedef struct TC0_struct
1765{
1766    register8_t CTRLA;  /* Control  Register A */
1767    register8_t CTRLB;  /* Control Register B */
1768    register8_t CTRLC;  /* Control register C */
1769    register8_t CTRLD;  /* Control Register D */
1770    register8_t CTRLE;  /* Control Register E */
1771    register8_t reserved_0x05;
1772    register8_t INTCTRLA;  /* Interrupt Control Register A */
1773    register8_t INTCTRLB;  /* Interrupt Control Register B */
1774    register8_t CTRLFCLR;  /* Control Register F Clear */
1775    register8_t CTRLFSET;  /* Control Register F Set */
1776    register8_t CTRLGCLR;  /* Control Register G Clear */
1777    register8_t CTRLGSET;  /* Control Register G Set */
1778    register8_t INTFLAGS;  /* Interrupt Flag Register */
1779    register8_t reserved_0x0D;
1780    register8_t reserved_0x0E;
1781    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1782    register8_t reserved_0x10;
1783    register8_t reserved_0x11;
1784    register8_t reserved_0x12;
1785    register8_t reserved_0x13;
1786    register8_t reserved_0x14;
1787    register8_t reserved_0x15;
1788    register8_t reserved_0x16;
1789    register8_t reserved_0x17;
1790    register8_t reserved_0x18;
1791    register8_t reserved_0x19;
1792    register8_t reserved_0x1A;
1793    register8_t reserved_0x1B;
1794    register8_t reserved_0x1C;
1795    register8_t reserved_0x1D;
1796    register8_t reserved_0x1E;
1797    register8_t reserved_0x1F;
1798    _WORDREGISTER(CNT);  /* Count */
1799    register8_t reserved_0x22;
1800    register8_t reserved_0x23;
1801    register8_t reserved_0x24;
1802    register8_t reserved_0x25;
1803    _WORDREGISTER(PER);  /* Period */
1804    _WORDREGISTER(CCA);  /* Compare or Capture A */
1805    _WORDREGISTER(CCB);  /* Compare or Capture B */
1806    _WORDREGISTER(CCC);  /* Compare or Capture C */
1807    _WORDREGISTER(CCD);  /* Compare or Capture D */
1808    register8_t reserved_0x30;
1809    register8_t reserved_0x31;
1810    register8_t reserved_0x32;
1811    register8_t reserved_0x33;
1812    register8_t reserved_0x34;
1813    register8_t reserved_0x35;
1814    _WORDREGISTER(PERBUF);  /* Period Buffer */
1815    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1816    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1817    _WORDREGISTER(CCCBUF);  /* Compare Or Capture C Buffer */
1818    _WORDREGISTER(CCDBUF);  /* Compare Or Capture D Buffer */
1819} TC0_t;
1820
1821/*
1822--------------------------------------------------------------------------
1823TC - 16-bit Timer/Counter With PWM
1824--------------------------------------------------------------------------
1825*/
1826
1827/* 16-bit Timer/Counter 1 */
1828typedef struct TC1_struct
1829{
1830    register8_t CTRLA;  /* Control  Register A */
1831    register8_t CTRLB;  /* Control Register B */
1832    register8_t CTRLC;  /* Control register C */
1833    register8_t CTRLD;  /* Control Register D */
1834    register8_t CTRLE;  /* Control Register E */
1835    register8_t reserved_0x05;
1836    register8_t INTCTRLA;  /* Interrupt Control Register A */
1837    register8_t INTCTRLB;  /* Interrupt Control Register B */
1838    register8_t CTRLFCLR;  /* Control Register F Clear */
1839    register8_t CTRLFSET;  /* Control Register F Set */
1840    register8_t CTRLGCLR;  /* Control Register G Clear */
1841    register8_t CTRLGSET;  /* Control Register G Set */
1842    register8_t INTFLAGS;  /* Interrupt Flag Register */
1843    register8_t reserved_0x0D;
1844    register8_t reserved_0x0E;
1845    register8_t TEMP;  /* Temporary Register For 16-bit Access */
1846    register8_t reserved_0x10;
1847    register8_t reserved_0x11;
1848    register8_t reserved_0x12;
1849    register8_t reserved_0x13;
1850    register8_t reserved_0x14;
1851    register8_t reserved_0x15;
1852    register8_t reserved_0x16;
1853    register8_t reserved_0x17;
1854    register8_t reserved_0x18;
1855    register8_t reserved_0x19;
1856    register8_t reserved_0x1A;
1857    register8_t reserved_0x1B;
1858    register8_t reserved_0x1C;
1859    register8_t reserved_0x1D;
1860    register8_t reserved_0x1E;
1861    register8_t reserved_0x1F;
1862    _WORDREGISTER(CNT);  /* Count */
1863    register8_t reserved_0x22;
1864    register8_t reserved_0x23;
1865    register8_t reserved_0x24;
1866    register8_t reserved_0x25;
1867    _WORDREGISTER(PER);  /* Period */
1868    _WORDREGISTER(CCA);  /* Compare or Capture A */
1869    _WORDREGISTER(CCB);  /* Compare or Capture B */
1870    register8_t reserved_0x2C;
1871    register8_t reserved_0x2D;
1872    register8_t reserved_0x2E;
1873    register8_t reserved_0x2F;
1874    register8_t reserved_0x30;
1875    register8_t reserved_0x31;
1876    register8_t reserved_0x32;
1877    register8_t reserved_0x33;
1878    register8_t reserved_0x34;
1879    register8_t reserved_0x35;
1880    _WORDREGISTER(PERBUF);  /* Period Buffer */
1881    _WORDREGISTER(CCABUF);  /* Compare Or Capture A Buffer */
1882    _WORDREGISTER(CCBBUF);  /* Compare Or Capture B Buffer */
1883} TC1_t;
1884
1885/*
1886--------------------------------------------------------------------------
1887TC - 16-bit Timer/Counter With PWM
1888--------------------------------------------------------------------------
1889*/
1890
1891/* Advanced Waveform Extension */
1892typedef struct AWEX_struct
1893{
1894    register8_t CTRL;  /* Control Register */
1895    register8_t reserved_0x01;
1896    register8_t FDEMASK;  /* Fault Detection Event Mask */
1897    register8_t FDCTRL;  /* Fault Detection Control Register */
1898    register8_t STATUS;  /* Status Register */
1899    register8_t reserved_0x05;
1900    register8_t DTBOTH;  /* Dead Time Both Sides */
1901    register8_t DTBOTHBUF;  /* Dead Time Both Sides Buffer */
1902    register8_t DTLS;  /* Dead Time Low Side */
1903    register8_t DTHS;  /* Dead Time High Side */
1904    register8_t DTLSBUF;  /* Dead Time Low Side Buffer */
1905    register8_t DTHSBUF;  /* Dead Time High Side Buffer */
1906    register8_t OUTOVEN;  /* Output Override Enable */
1907} AWEX_t;
1908
1909/*
1910--------------------------------------------------------------------------
1911TC - 16-bit Timer/Counter With PWM
1912--------------------------------------------------------------------------
1913*/
1914
1915/* High-Resolution Extension */
1916typedef struct HIRES_struct
1917{
1918    register8_t CTRLA;  /* Control Register */
1919} HIRES_t;
1920
1921/* Clock Selection */
1922typedef enum TC_CLKSEL_enum
1923{
1924    TC_CLKSEL_OFF_gc = (0x00<<0),  /* Timer Off */
1925    TC_CLKSEL_DIV1_gc = (0x01<<0),  /* System Clock */
1926    TC_CLKSEL_DIV2_gc = (0x02<<0),  /* System Clock / 2 */
1927    TC_CLKSEL_DIV4_gc = (0x03<<0),  /* System Clock / 4 */
1928    TC_CLKSEL_DIV8_gc = (0x04<<0),  /* System Clock / 8 */
1929    TC_CLKSEL_DIV64_gc = (0x05<<0),  /* System Clock / 64 */
1930    TC_CLKSEL_DIV256_gc = (0x06<<0),  /* System Clock / 256 */
1931    TC_CLKSEL_DIV1024_gc = (0x07<<0),  /* System Clock / 1024 */
1932    TC_CLKSEL_EVCH0_gc = (0x08<<0),  /* Event Channel 0 */
1933    TC_CLKSEL_EVCH1_gc = (0x09<<0),  /* Event Channel 1 */
1934    TC_CLKSEL_EVCH2_gc = (0x0A<<0),  /* Event Channel 2 */
1935    TC_CLKSEL_EVCH3_gc = (0x0B<<0),  /* Event Channel 3 */
1936    TC_CLKSEL_EVCH4_gc = (0x0C<<0),  /* Event Channel 4 */
1937    TC_CLKSEL_EVCH5_gc = (0x0D<<0),  /* Event Channel 5 */
1938    TC_CLKSEL_EVCH6_gc = (0x0E<<0),  /* Event Channel 6 */
1939    TC_CLKSEL_EVCH7_gc = (0x0F<<0),  /* Event Channel 7 */
1940} TC_CLKSEL_t;
1941
1942/* Waveform Generation Mode */
1943typedef enum TC_WGMODE_enum
1944{
1945    TC_WGMODE_NORMAL_gc = (0x00<<0),  /* Normal Mode */
1946    TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
1947    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
1948    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
1949    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
1950    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
1951} TC_WGMODE_t;
1952
1953/* Event Action */
1954typedef enum TC_EVACT_enum
1955{
1956    TC_EVACT_OFF_gc = (0x00<<5),  /* No Event Action */
1957    TC_EVACT_CAPT_gc = (0x01<<5),  /* Input Capture */
1958    TC_EVACT_UPDOWN_gc = (0x02<<5),  /* Externally Controlled Up/Down Count */
1959    TC_EVACT_QDEC_gc = (0x03<<5),  /* Quadrature Decode */
1960    TC_EVACT_RESTART_gc = (0x04<<5),  /* Restart */
1961    TC_EVACT_FRW_gc = (0x05<<5),  /* Frequency Capture */
1962    TC_EVACT_PW_gc = (0x06<<5),  /* Pulse-width Capture */
1963} TC_EVACT_t;
1964
1965/* Event Selection */
1966typedef enum TC_EVSEL_enum
1967{
1968    TC_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
1969    TC_EVSEL_CH0_gc = (0x08<<0),  /* Event Channel 0 */
1970    TC_EVSEL_CH1_gc = (0x09<<0),  /* Event Channel 1 */
1971    TC_EVSEL_CH2_gc = (0x0A<<0),  /* Event Channel 2 */
1972    TC_EVSEL_CH3_gc = (0x0B<<0),  /* Event Channel 3 */
1973    TC_EVSEL_CH4_gc = (0x0C<<0),  /* Event Channel 4 */
1974    TC_EVSEL_CH5_gc = (0x0D<<0),  /* Event Channel 5 */
1975    TC_EVSEL_CH6_gc = (0x0E<<0),  /* Event Channel 6 */
1976    TC_EVSEL_CH7_gc = (0x0F<<0),  /* Event Channel 7 */
1977} TC_EVSEL_t;
1978
1979/* Error Interrupt Level */
1980typedef enum TC_ERRINTLVL_enum
1981{
1982    TC_ERRINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
1983    TC_ERRINTLVL_LO_gc = (0x01<<2),  /* Low Level */
1984    TC_ERRINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
1985    TC_ERRINTLVL_HI_gc = (0x03<<2),  /* High Level */
1986} TC_ERRINTLVL_t;
1987
1988/* Overflow Interrupt Level */
1989typedef enum TC_OVFINTLVL_enum
1990{
1991    TC_OVFINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
1992    TC_OVFINTLVL_LO_gc = (0x01<<0),  /* Low Level */
1993    TC_OVFINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
1994    TC_OVFINTLVL_HI_gc = (0x03<<0),  /* High Level */
1995} TC_OVFINTLVL_t;
1996
1997/* Compare or Capture D Interrupt Level */
1998typedef enum TC_CCDINTLVL_enum
1999{
2000    TC_CCDINTLVL_OFF_gc = (0x00<<6),  /* Interrupt Disabled */
2001    TC_CCDINTLVL_LO_gc = (0x01<<6),  /* Low Level */
2002    TC_CCDINTLVL_MED_gc = (0x02<<6),  /* Medium Level */
2003    TC_CCDINTLVL_HI_gc = (0x03<<6),  /* High Level */
2004} TC_CCDINTLVL_t;
2005
2006/* Compare or Capture C Interrupt Level */
2007typedef enum TC_CCCINTLVL_enum
2008{
2009    TC_CCCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
2010    TC_CCCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
2011    TC_CCCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
2012    TC_CCCINTLVL_HI_gc = (0x03<<4),  /* High Level */
2013} TC_CCCINTLVL_t;
2014
2015/* Compare or Capture B Interrupt Level */
2016typedef enum TC_CCBINTLVL_enum
2017{
2018    TC_CCBINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
2019    TC_CCBINTLVL_LO_gc = (0x01<<2),  /* Low Level */
2020    TC_CCBINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
2021    TC_CCBINTLVL_HI_gc = (0x03<<2),  /* High Level */
2022} TC_CCBINTLVL_t;
2023
2024/* Compare or Capture A Interrupt Level */
2025typedef enum TC_CCAINTLVL_enum
2026{
2027    TC_CCAINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2028    TC_CCAINTLVL_LO_gc = (0x01<<0),  /* Low Level */
2029    TC_CCAINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2030    TC_CCAINTLVL_HI_gc = (0x03<<0),  /* High Level */
2031} TC_CCAINTLVL_t;
2032
2033/* Timer/Counter Command */
2034typedef enum TC_CMD_enum
2035{
2036    TC_CMD_NONE_gc = (0x00<<2),  /* No Command */
2037    TC_CMD_UPDATE_gc = (0x01<<2),  /* Force Update */
2038    TC_CMD_RESTART_gc = (0x02<<2),  /* Force Restart */
2039    TC_CMD_RESET_gc = (0x03<<2),  /* Force Hard Reset */
2040} TC_CMD_t;
2041
2042/* Fault Detect Action */
2043typedef enum AWEX_FDACT_enum
2044{
2045    AWEX_FDACT_NONE_gc = (0x00<<0),  /* No Fault Protection */
2046    AWEX_FDACT_CLEAROE_gc = (0x01<<0),  /* Clear Output Enable Bits */
2047    AWEX_FDACT_CLEARDIR_gc = (0x03<<0),  /* Clear I/O Port Direction Bits */
2048} AWEX_FDACT_t;
2049
2050/* High Resolution Enable */
2051typedef enum HIRES_HREN_enum
2052{
2053    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
2054    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
2055    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
2056    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
2057} HIRES_HREN_t;
2058
2059
2060/*
2061--------------------------------------------------------------------------
2062USART - Universal Asynchronous Receiver-Transmitter
2063--------------------------------------------------------------------------
2064*/
2065
2066/* Universal Synchronous/Asynchronous Receiver/Transmitter */
2067typedef struct USART_struct
2068{
2069    register8_t DATA;  /* Data Register */
2070    register8_t STATUS;  /* Status Register */
2071    register8_t reserved_0x02;
2072    register8_t CTRLA;  /* Control Register A */
2073    register8_t CTRLB;  /* Control Register B */
2074    register8_t CTRLC;  /* Control Register C */
2075    register8_t BAUDCTRLA;  /* Baud Rate Control Register A */
2076    register8_t BAUDCTRLB;  /* Baud Rate Control Register B */
2077} USART_t;
2078
2079/* Receive Complete Interrupt level */
2080typedef enum USART_RXCINTLVL_enum
2081{
2082    USART_RXCINTLVL_OFF_gc = (0x00<<4),  /* Interrupt Disabled */
2083    USART_RXCINTLVL_LO_gc = (0x01<<4),  /* Low Level */
2084    USART_RXCINTLVL_MED_gc = (0x02<<4),  /* Medium Level */
2085    USART_RXCINTLVL_HI_gc = (0x03<<4),  /* High Level */
2086} USART_RXCINTLVL_t;
2087
2088/* Transmit Complete Interrupt level */
2089typedef enum USART_TXCINTLVL_enum
2090{
2091    USART_TXCINTLVL_OFF_gc = (0x00<<2),  /* Interrupt Disabled */
2092    USART_TXCINTLVL_LO_gc = (0x01<<2),  /* Low Level */
2093    USART_TXCINTLVL_MED_gc = (0x02<<2),  /* Medium Level */
2094    USART_TXCINTLVL_HI_gc = (0x03<<2),  /* High Level */
2095} USART_TXCINTLVL_t;
2096
2097/* Data Register Empty Interrupt level */
2098typedef enum USART_DREINTLVL_enum
2099{
2100    USART_DREINTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2101    USART_DREINTLVL_LO_gc = (0x01<<0),  /* Low Level */
2102    USART_DREINTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2103    USART_DREINTLVL_HI_gc = (0x03<<0),  /* High Level */
2104} USART_DREINTLVL_t;
2105
2106/* Character Size */
2107typedef enum USART_CHSIZE_enum
2108{
2109    USART_CHSIZE_5BIT_gc = (0x00<<0),  /* Character size: 5 bit */
2110    USART_CHSIZE_6BIT_gc = (0x01<<0),  /* Character size: 6 bit */
2111    USART_CHSIZE_7BIT_gc = (0x02<<0),  /* Character size: 7 bit */
2112    USART_CHSIZE_8BIT_gc = (0x03<<0),  /* Character size: 8 bit */
2113    USART_CHSIZE_9BIT_gc = (0x07<<0),  /* Character size: 9 bit */
2114} USART_CHSIZE_t;
2115
2116/* Communication Mode */
2117typedef enum USART_CMODE_enum
2118{
2119    USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),  /* Asynchronous Mode */
2120    USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),  /* Synchronous Mode */
2121    USART_CMODE_IRDA_gc = (0x02<<6),  /* IrDA Mode */
2122    USART_CMODE_MSPI_gc = (0x03<<6),  /* Master SPI Mode */
2123} USART_CMODE_t;
2124
2125/* Parity Mode */
2126typedef enum USART_PMODE_enum
2127{
2128    USART_PMODE_DISABLED_gc = (0x00<<4),  /* No Parity */
2129    USART_PMODE_EVEN_gc = (0x02<<4),  /* Even Parity */
2130    USART_PMODE_ODD_gc = (0x03<<4),  /* Odd Parity */
2131} USART_PMODE_t;
2132
2133
2134/*
2135--------------------------------------------------------------------------
2136SPI - Serial Peripheral Interface
2137--------------------------------------------------------------------------
2138*/
2139
2140/* Serial Peripheral Interface */
2141typedef struct SPI_struct
2142{
2143    register8_t CTRL;  /* Control Register */
2144    register8_t INTCTRL;  /* Interrupt Control Register */
2145    register8_t STATUS;  /* Status Register */
2146    register8_t DATA;  /* Data Register */
2147} SPI_t;
2148
2149/* SPI Mode */
2150typedef enum SPI_MODE_enum
2151{
2152    SPI_MODE_0_gc = (0x00<<2),  /* SPI Mode 0 */
2153    SPI_MODE_1_gc = (0x01<<2),  /* SPI Mode 1 */
2154    SPI_MODE_2_gc = (0x02<<2),  /* SPI Mode 2 */
2155    SPI_MODE_3_gc = (0x03<<2),  /* SPI Mode 3 */
2156} SPI_MODE_t;
2157
2158/* Prescaler setting */
2159typedef enum SPI_PRESCALER_enum
2160{
2161    SPI_PRESCALER_DIV4_gc = (0x00<<0),  /* System Clock / 4 */
2162    SPI_PRESCALER_DIV16_gc = (0x01<<0),  /* System Clock / 16 */
2163    SPI_PRESCALER_DIV64_gc = (0x02<<0),  /* System Clock / 64 */
2164    SPI_PRESCALER_DIV128_gc = (0x03<<0),  /* System Clock / 128 */
2165} SPI_PRESCALER_t;
2166
2167/* Interrupt level */
2168typedef enum SPI_INTLVL_enum
2169{
2170    SPI_INTLVL_OFF_gc = (0x00<<0),  /* Interrupt Disabled */
2171    SPI_INTLVL_LO_gc = (0x01<<0),  /* Low Level */
2172    SPI_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
2173    SPI_INTLVL_HI_gc = (0x03<<0),  /* High Level */
2174} SPI_INTLVL_t;
2175
2176
2177/*
2178--------------------------------------------------------------------------
2179IRCOM - IR Communication Module
2180--------------------------------------------------------------------------
2181*/
2182
2183/* IR Communication Module */
2184typedef struct IRCOM_struct
2185{
2186    register8_t CTRL;  /* Control Register */
2187    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
2188    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
2189} IRCOM_t;
2190
2191/* Event channel selection */
2192typedef enum IRDA_EVSEL_enum
2193{
2194    IRDA_EVSEL_OFF_gc = (0x00<<0),  /* No Event Source */
2195    IRDA_EVSEL_0_gc = (0x08<<0),  /* Event Channel 0 */
2196    IRDA_EVSEL_1_gc = (0x09<<0),  /* Event Channel 1 */
2197    IRDA_EVSEL_2_gc = (0x0A<<0),  /* Event Channel 2 */
2198    IRDA_EVSEL_3_gc = (0x0B<<0),  /* Event Channel 3 */
2199    IRDA_EVSEL_4_gc = (0x0C<<0),  /* Event Channel 4 */
2200    IRDA_EVSEL_5_gc = (0x0D<<0),  /* Event Channel 5 */
2201    IRDA_EVSEL_6_gc = (0x0E<<0),  /* Event Channel 6 */
2202    IRDA_EVSEL_7_gc = (0x0F<<0),  /* Event Channel 7 */
2203} IRDA_EVSEL_t;
2204
2205
2206
2207/*
2208==========================================================================
2209IO Module Instances. Mapped to memory.
2210==========================================================================
2211*/
2212
2213#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
2214#define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
2215#define VPORT2    (*(VPORT_t *) 0x0018)  /* Virtual Port 2 */
2216#define VPORT3    (*(VPORT_t *) 0x001C)  /* Virtual Port 3 */
2217#define OCD    (*(OCD_t *) 0x002E)  /* On-Chip Debug System */
2218#define CLK    (*(CLK_t *) 0x0040)  /* Clock System */
2219#define SLEEP    (*(SLEEP_t *) 0x0048)  /* Sleep Controller */
2220#define OSC    (*(OSC_t *) 0x0050)  /* Oscillator Control */
2221#define DFLLRC32M    (*(DFLL_t *) 0x0060)  /* DFLL for 32MHz RC Oscillator */
2222#define DFLLRC2M    (*(DFLL_t *) 0x0068)  /* DFLL for 2MHz RC Oscillator */
2223#define PR    (*(PR_t *) 0x0070)  /* Power Reduction */
2224#define RST    (*(RST_t *) 0x0078)  /* Reset Controller */
2225#define WDT    (*(WDT_t *) 0x0080)  /* Watch-Dog Timer */
2226#define MCU    (*(MCU_t *) 0x0090)  /* MCU Control */
2227#define PMIC    (*(PMIC_t *) 0x00A0)  /* Programmable Interrupt Controller */
2228#define PORTCFG    (*(PORTCFG_t *) 0x00B0)  /* Port Configuration */
2229#define EVSYS    (*(EVSYS_t *) 0x0180)  /* Event System */
2230#define NVM    (*(NVM_t *) 0x01C0)  /* Non Volatile Memory Controller */
2231#define ADCA    (*(ADC_t *) 0x0200)  /* Analog to Digital Converter A */
2232#define DACB    (*(DAC_t *) 0x0320)  /* Digital to Analog Converter B */
2233#define ACA    (*(AC_t *) 0x0380)  /* Analog Comparator A */
2234#define RTC    (*(RTC_t *) 0x0400)  /* Real-Time Counter */
2235#define TWIC    (*(TWI_t *) 0x0480)  /* Two-Wire Interface C */
2236#define TWIE    (*(TWI_t *) 0x04A0)  /* Two-Wire Interface E */
2237#define PORTA    (*(PORT_t *) 0x0600)  /* Port A */
2238#define PORTB    (*(PORT_t *) 0x0620)  /* Port B */
2239#define PORTC    (*(PORT_t *) 0x0640)  /* Port C */
2240#define PORTD    (*(PORT_t *) 0x0660)  /* Port D */
2241#define PORTE    (*(PORT_t *) 0x0680)  /* Port E */
2242#define PORTR    (*(PORT_t *) 0x07E0)  /* Port R */
2243#define TCC0    (*(TC0_t *) 0x0800)  /* Timer/Counter C0 */
2244#define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
2245#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
2246#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
2247#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
2248#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
2249#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
2250#define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
2251#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
2252#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
2253#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
2254
2255
2256#endif /* !defined (__ASSEMBLER__) */
2257
2258
2259/* ========== Flattened fully qualified IO register names ========== */
2260
2261/* GPIO - General Purpose IO Registers */
2262#define GPIO_GPIO0  _SFR_MEM8(0x0000)
2263#define GPIO_GPIO1  _SFR_MEM8(0x0001)
2264#define GPIO_GPIO2  _SFR_MEM8(0x0002)
2265#define GPIO_GPIO3  _SFR_MEM8(0x0003)
2266#define GPIO_GPIO4  _SFR_MEM8(0x0004)
2267#define GPIO_GPIO5  _SFR_MEM8(0x0005)
2268#define GPIO_GPIO6  _SFR_MEM8(0x0006)
2269#define GPIO_GPIO7  _SFR_MEM8(0x0007)
2270#define GPIO_GPIO8  _SFR_MEM8(0x0008)
2271#define GPIO_GPIO9  _SFR_MEM8(0x0009)
2272#define GPIO_GPIOA  _SFR_MEM8(0x000A)
2273#define GPIO_GPIOB  _SFR_MEM8(0x000B)
2274#define GPIO_GPIOC  _SFR_MEM8(0x000C)
2275#define GPIO_GPIOD  _SFR_MEM8(0x000D)
2276#define GPIO_GPIOE  _SFR_MEM8(0x000E)
2277#define GPIO_GPIOF  _SFR_MEM8(0x000F)
2278
2279/* VPORT0 - Virtual Port 0 */
2280#define VPORT0_DIR  _SFR_MEM8(0x0010)
2281#define VPORT0_OUT  _SFR_MEM8(0x0011)
2282#define VPORT0_IN  _SFR_MEM8(0x0012)
2283#define VPORT0_INTFLAGS  _SFR_MEM8(0x0013)
2284
2285/* VPORT1 - Virtual Port 1 */
2286#define VPORT1_DIR  _SFR_MEM8(0x0014)
2287#define VPORT1_OUT  _SFR_MEM8(0x0015)
2288#define VPORT1_IN  _SFR_MEM8(0x0016)
2289#define VPORT1_INTFLAGS  _SFR_MEM8(0x0017)
2290
2291/* VPORT2 - Virtual Port 2 */
2292#define VPORT2_DIR  _SFR_MEM8(0x0018)
2293#define VPORT2_OUT  _SFR_MEM8(0x0019)
2294#define VPORT2_IN  _SFR_MEM8(0x001A)
2295#define VPORT2_INTFLAGS  _SFR_MEM8(0x001B)
2296
2297/* VPORT3 - Virtual Port 3 */
2298#define VPORT3_DIR  _SFR_MEM8(0x001C)
2299#define VPORT3_OUT  _SFR_MEM8(0x001D)
2300#define VPORT3_IN  _SFR_MEM8(0x001E)
2301#define VPORT3_INTFLAGS  _SFR_MEM8(0x001F)
2302
2303/* OCD - On-Chip Debug System */
2304#define OCD_OCDR0  _SFR_MEM8(0x002E)
2305#define OCD_OCDR1  _SFR_MEM8(0x002F)
2306
2307/* CPU - CPU Registers */
2308#define CPU_CCP  _SFR_MEM8(0x0034)
2309#define CPU_RAMPD  _SFR_MEM8(0x0038)
2310#define CPU_RAMPX  _SFR_MEM8(0x0039)
2311#define CPU_RAMPY  _SFR_MEM8(0x003A)
2312#define CPU_RAMPZ  _SFR_MEM8(0x003B)
2313#define CPU_EIND  _SFR_MEM8(0x003C)
2314#define CPU_SPL  _SFR_MEM8(0x003D)
2315#define CPU_SPH  _SFR_MEM8(0x003E)
2316#define CPU_SREG  _SFR_MEM8(0x003F)
2317
2318/* CLK - Clock System */
2319#define CLK_CTRL  _SFR_MEM8(0x0040)
2320#define CLK_PSCTRL  _SFR_MEM8(0x0041)
2321#define CLK_LOCK  _SFR_MEM8(0x0042)
2322#define CLK_RTCCTRL  _SFR_MEM8(0x0043)
2323
2324/* SLEEP - Sleep Controller */
2325#define SLEEP_CTRL  _SFR_MEM8(0x0048)
2326
2327/* OSC - Oscillator Control */
2328#define OSC_CTRL  _SFR_MEM8(0x0050)
2329#define OSC_STATUS  _SFR_MEM8(0x0051)
2330#define OSC_XOSCCTRL  _SFR_MEM8(0x0052)
2331#define OSC_XOSCFAIL  _SFR_MEM8(0x0053)
2332#define OSC_RC32KCAL  _SFR_MEM8(0x0054)
2333#define OSC_PLLCTRL  _SFR_MEM8(0x0055)
2334#define OSC_DFLLCTRL  _SFR_MEM8(0x0056)
2335
2336/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
2337#define DFLLRC32M_CTRL  _SFR_MEM8(0x0060)
2338#define DFLLRC32M_CALA  _SFR_MEM8(0x0062)
2339#define DFLLRC32M_CALB  _SFR_MEM8(0x0063)
2340#define DFLLRC32M_COMP0  _SFR_MEM8(0x0064)
2341#define DFLLRC32M_COMP1  _SFR_MEM8(0x0065)
2342#define DFLLRC32M_COMP2  _SFR_MEM8(0x0066)
2343
2344/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
2345#define DFLLRC2M_CTRL  _SFR_MEM8(0x0068)
2346#define DFLLRC2M_CALA  _SFR_MEM8(0x006A)
2347#define DFLLRC2M_CALB  _SFR_MEM8(0x006B)
2348#define DFLLRC2M_COMP0  _SFR_MEM8(0x006C)
2349#define DFLLRC2M_COMP1  _SFR_MEM8(0x006D)
2350#define DFLLRC2M_COMP2  _SFR_MEM8(0x006E)
2351
2352/* PR - Power Reduction */
2353#define PR_PRGEN  _SFR_MEM8(0x0070)
2354#define PR_PRPA  _SFR_MEM8(0x0071)
2355#define PR_PRPB  _SFR_MEM8(0x0072)
2356#define PR_PRPC  _SFR_MEM8(0x0073)
2357#define PR_PRPD  _SFR_MEM8(0x0074)
2358#define PR_PRPE  _SFR_MEM8(0x0075)
2359#define PR_PRPF  _SFR_MEM8(0x0076)
2360
2361/* RST - Reset Controller */
2362#define RST_STATUS  _SFR_MEM8(0x0078)
2363#define RST_CTRL  _SFR_MEM8(0x0079)
2364
2365/* WDT - Watch-Dog Timer */
2366#define WDT_CTRL  _SFR_MEM8(0x0080)
2367#define WDT_WINCTRL  _SFR_MEM8(0x0081)
2368#define WDT_STATUS  _SFR_MEM8(0x0082)
2369
2370/* MCU - MCU Control */
2371#define MCU_DEVID0  _SFR_MEM8(0x0090)
2372#define MCU_DEVID1  _SFR_MEM8(0x0091)
2373#define MCU_DEVID2  _SFR_MEM8(0x0092)
2374#define MCU_REVID  _SFR_MEM8(0x0093)
2375#define MCU_JTAGUID  _SFR_MEM8(0x0094)
2376#define MCU_MCUCR  _SFR_MEM8(0x0096)
2377#define MCU_EVSYSLOCK  _SFR_MEM8(0x0098)
2378#define MCU_AWEXLOCK  _SFR_MEM8(0x0099)
2379
2380/* PMIC - Programmable Interrupt Controller */
2381#define PMIC_STATUS  _SFR_MEM8(0x00A0)
2382#define PMIC_INTPRI  _SFR_MEM8(0x00A1)
2383#define PMIC_CTRL  _SFR_MEM8(0x00A2)
2384
2385/* PORTCFG - Port Configuration */
2386#define PORTCFG_MPCMASK  _SFR_MEM8(0x00B0)
2387#define PORTCFG_VPCTRLA  _SFR_MEM8(0x00B2)
2388#define PORTCFG_VPCTRLB  _SFR_MEM8(0x00B3)
2389#define PORTCFG_CLKEVOUT  _SFR_MEM8(0x00B4)
2390
2391/* EVSYS - Event System */
2392#define EVSYS_CH0MUX  _SFR_MEM8(0x0180)
2393#define EVSYS_CH1MUX  _SFR_MEM8(0x0181)
2394#define EVSYS_CH2MUX  _SFR_MEM8(0x0182)
2395#define EVSYS_CH3MUX  _SFR_MEM8(0x0183)
2396#define EVSYS_CH0CTRL  _SFR_MEM8(0x0188)
2397#define EVSYS_CH1CTRL  _SFR_MEM8(0x0189)
2398#define EVSYS_CH2CTRL  _SFR_MEM8(0x018A)
2399#define EVSYS_CH3CTRL  _SFR_MEM8(0x018B)
2400#define EVSYS_STROBE  _SFR_MEM8(0x0190)
2401#define EVSYS_DATA  _SFR_MEM8(0x0191)
2402
2403/* NVM - Non Volatile Memory Controller */
2404#define NVM_ADDR0  _SFR_MEM8(0x01C0)
2405#define NVM_ADDR1  _SFR_MEM8(0x01C1)
2406#define NVM_ADDR2  _SFR_MEM8(0x01C2)
2407#define NVM_DATA0  _SFR_MEM8(0x01C4)
2408#define NVM_DATA1  _SFR_MEM8(0x01C5)
2409#define NVM_DATA2  _SFR_MEM8(0x01C6)
2410#define NVM_CMD  _SFR_MEM8(0x01CA)
2411#define NVM_CTRLA  _SFR_MEM8(0x01CB)
2412#define NVM_CTRLB  _SFR_MEM8(0x01CC)
2413#define NVM_INTCTRL  _SFR_MEM8(0x01CD)
2414#define NVM_STATUS  _SFR_MEM8(0x01CF)
2415#define NVM_LOCKBITS  _SFR_MEM8(0x01D0)
2416
2417/* ADCA - Analog to Digital Converter A */
2418#define ADCA_CTRLA  _SFR_MEM8(0x0200)
2419#define ADCA_CTRLB  _SFR_MEM8(0x0201)
2420#define ADCA_REFCTRL  _SFR_MEM8(0x0202)
2421#define ADCA_EVCTRL  _SFR_MEM8(0x0203)
2422#define ADCA_PRESCALER  _SFR_MEM8(0x0204)
2423#define ADCA_INTFLAGS  _SFR_MEM8(0x0206)
2424#define ADCA_CAL  _SFR_MEM16(0x020C)
2425#define ADCA_CH0RES  _SFR_MEM16(0x0210)
2426#define ADCA_CMP  _SFR_MEM16(0x0218)
2427#define ADCA_CH0_CTRL  _SFR_MEM8(0x0220)
2428#define ADCA_CH0_MUXCTRL  _SFR_MEM8(0x0221)
2429#define ADCA_CH0_INTCTRL  _SFR_MEM8(0x0222)
2430#define ADCA_CH0_INTFLAGS  _SFR_MEM8(0x0223)
2431#define ADCA_CH0_RES  _SFR_MEM16(0x0224)
2432
2433/* DACB - Digital to Analog Converter B */
2434
2435/* ACA - Analog Comparator A */
2436#define ACA_AC0CTRL  _SFR_MEM8(0x0380)
2437#define ACA_AC1CTRL  _SFR_MEM8(0x0381)
2438#define ACA_AC0MUXCTRL  _SFR_MEM8(0x0382)
2439#define ACA_AC1MUXCTRL  _SFR_MEM8(0x0383)
2440#define ACA_CTRLA  _SFR_MEM8(0x0384)
2441#define ACA_CTRLB  _SFR_MEM8(0x0385)
2442#define ACA_WINCTRL  _SFR_MEM8(0x0386)
2443#define ACA_STATUS  _SFR_MEM8(0x0387)
2444
2445/* RTC - Real-Time Counter */
2446#define RTC_CTRL  _SFR_MEM8(0x0400)
2447#define RTC_STATUS  _SFR_MEM8(0x0401)
2448#define RTC_INTCTRL  _SFR_MEM8(0x0402)
2449#define RTC_INTFLAGS  _SFR_MEM8(0x0403)
2450#define RTC_TEMP  _SFR_MEM8(0x0404)
2451#define RTC_CNT  _SFR_MEM16(0x0408)
2452#define RTC_PER  _SFR_MEM16(0x040A)
2453#define RTC_COMP  _SFR_MEM16(0x040C)
2454
2455/* TWIC - Two-Wire Interface C */
2456#define TWIC_CTRL  _SFR_MEM8(0x0480)
2457#define TWIC_MASTER_CTRLA  _SFR_MEM8(0x0481)
2458#define TWIC_MASTER_CTRLB  _SFR_MEM8(0x0482)
2459#define TWIC_MASTER_CTRLC  _SFR_MEM8(0x0483)
2460#define TWIC_MASTER_STATUS  _SFR_MEM8(0x0484)
2461#define TWIC_MASTER_BAUD  _SFR_MEM8(0x0485)
2462#define TWIC_MASTER_ADDR  _SFR_MEM8(0x0486)
2463#define TWIC_MASTER_DATA  _SFR_MEM8(0x0487)
2464#define TWIC_SLAVE_CTRLA  _SFR_MEM8(0x0488)
2465#define TWIC_SLAVE_CTRLB  _SFR_MEM8(0x0489)
2466#define TWIC_SLAVE_STATUS  _SFR_MEM8(0x048A)
2467#define TWIC_SLAVE_ADDR  _SFR_MEM8(0x048B)
2468#define TWIC_SLAVE_DATA  _SFR_MEM8(0x048C)
2469#define TWIC_SLAVE_ADDRMASK  _SFR_MEM8(0x048D)
2470
2471/* TWIE - Two-Wire Interface E */
2472#define TWIE_CTRL  _SFR_MEM8(0x04A0)
2473#define TWIE_MASTER_CTRLA  _SFR_MEM8(0x04A1)
2474#define TWIE_MASTER_CTRLB  _SFR_MEM8(0x04A2)
2475#define TWIE_MASTER_CTRLC  _SFR_MEM8(0x04A3)
2476#define TWIE_MASTER_STATUS  _SFR_MEM8(0x04A4)
2477#define TWIE_MASTER_BAUD  _SFR_MEM8(0x04A5)
2478#define TWIE_MASTER_ADDR  _SFR_MEM8(0x04A6)
2479#define TWIE_MASTER_DATA  _SFR_MEM8(0x04A7)
2480#define TWIE_SLAVE_CTRLA  _SFR_MEM8(0x04A8)
2481#define TWIE_SLAVE_CTRLB  _SFR_MEM8(0x04A9)
2482#define TWIE_SLAVE_STATUS  _SFR_MEM8(0x04AA)
2483#define TWIE_SLAVE_ADDR  _SFR_MEM8(0x04AB)
2484#define TWIE_SLAVE_DATA  _SFR_MEM8(0x04AC)
2485#define TWIE_SLAVE_ADDRMASK  _SFR_MEM8(0x04AD)
2486
2487
2488/* PORTA - Port A */
2489#define PORTA_DIR  _SFR_MEM8(0x0600)
2490#define PORTA_DIRSET  _SFR_MEM8(0x0601)
2491#define PORTA_DIRCLR  _SFR_MEM8(0x0602)
2492#define PORTA_DIRTGL  _SFR_MEM8(0x0603)
2493#define PORTA_OUT  _SFR_MEM8(0x0604)
2494#define PORTA_OUTSET  _SFR_MEM8(0x0605)
2495#define PORTA_OUTCLR  _SFR_MEM8(0x0606)
2496#define PORTA_OUTTGL  _SFR_MEM8(0x0607)
2497#define PORTA_IN  _SFR_MEM8(0x0608)
2498#define PORTA_INTCTRL  _SFR_MEM8(0x0609)
2499#define PORTA_INT0MASK  _SFR_MEM8(0x060A)
2500#define PORTA_INT1MASK  _SFR_MEM8(0x060B)
2501#define PORTA_INTFLAGS  _SFR_MEM8(0x060C)
2502#define PORTA_PIN0CTRL  _SFR_MEM8(0x0610)
2503#define PORTA_PIN1CTRL  _SFR_MEM8(0x0611)
2504#define PORTA_PIN2CTRL  _SFR_MEM8(0x0612)
2505#define PORTA_PIN3CTRL  _SFR_MEM8(0x0613)
2506#define PORTA_PIN4CTRL  _SFR_MEM8(0x0614)
2507#define PORTA_PIN5CTRL  _SFR_MEM8(0x0615)
2508#define PORTA_PIN6CTRL  _SFR_MEM8(0x0616)
2509#define PORTA_PIN7CTRL  _SFR_MEM8(0x0617)
2510
2511/* PORTB - Port B */
2512#define PORTB_DIR  _SFR_MEM8(0x0620)
2513#define PORTB_DIRSET  _SFR_MEM8(0x0621)
2514#define PORTB_DIRCLR  _SFR_MEM8(0x0622)
2515#define PORTB_DIRTGL  _SFR_MEM8(0x0623)
2516#define PORTB_OUT  _SFR_MEM8(0x0624)
2517#define PORTB_OUTSET  _SFR_MEM8(0x0625)
2518#define PORTB_OUTCLR  _SFR_MEM8(0x0626)
2519#define PORTB_OUTTGL  _SFR_MEM8(0x0627)
2520#define PORTB_IN  _SFR_MEM8(0x0628)
2521#define PORTB_INTCTRL  _SFR_MEM8(0x0629)
2522#define PORTB_INT0MASK  _SFR_MEM8(0x062A)
2523#define PORTB_INT1MASK  _SFR_MEM8(0x062B)
2524#define PORTB_INTFLAGS  _SFR_MEM8(0x062C)
2525#define PORTB_PIN0CTRL  _SFR_MEM8(0x0630)
2526#define PORTB_PIN1CTRL  _SFR_MEM8(0x0631)
2527#define PORTB_PIN2CTRL  _SFR_MEM8(0x0632)
2528#define PORTB_PIN3CTRL  _SFR_MEM8(0x0633)
2529#define PORTB_PIN4CTRL  _SFR_MEM8(0x0634)
2530#define PORTB_PIN5CTRL  _SFR_MEM8(0x0635)
2531#define PORTB_PIN6CTRL  _SFR_MEM8(0x0636)
2532#define PORTB_PIN7CTRL  _SFR_MEM8(0x0637)
2533
2534/* PORTC - Port C */
2535#define PORTC_DIR  _SFR_MEM8(0x0640)
2536#define PORTC_DIRSET  _SFR_MEM8(0x0641)
2537#define PORTC_DIRCLR  _SFR_MEM8(0x0642)
2538#define PORTC_DIRTGL  _SFR_MEM8(0x0643)
2539#define PORTC_OUT  _SFR_MEM8(0x0644)
2540#define PORTC_OUTSET  _SFR_MEM8(0x0645)
2541#define PORTC_OUTCLR  _SFR_MEM8(0x0646)
2542#define PORTC_OUTTGL  _SFR_MEM8(0x0647)
2543#define PORTC_IN  _SFR_MEM8(0x0648)
2544#define PORTC_INTCTRL  _SFR_MEM8(0x0649)
2545#define PORTC_INT0MASK  _SFR_MEM8(0x064A)
2546#define PORTC_INT1MASK  _SFR_MEM8(0x064B)
2547#define PORTC_INTFLAGS  _SFR_MEM8(0x064C)
2548#define PORTC_PIN0CTRL  _SFR_MEM8(0x0650)
2549#define PORTC_PIN1CTRL  _SFR_MEM8(0x0651)
2550#define PORTC_PIN2CTRL  _SFR_MEM8(0x0652)
2551#define PORTC_PIN3CTRL  _SFR_MEM8(0x0653)
2552#define PORTC_PIN4CTRL  _SFR_MEM8(0x0654)
2553#define PORTC_PIN5CTRL  _SFR_MEM8(0x0655)
2554#define PORTC_PIN6CTRL  _SFR_MEM8(0x0656)
2555#define PORTC_PIN7CTRL  _SFR_MEM8(0x0657)
2556
2557/* PORTD - Port D */
2558#define PORTD_DIR  _SFR_MEM8(0x0660)
2559#define PORTD_DIRSET  _SFR_MEM8(0x0661)
2560#define PORTD_DIRCLR  _SFR_MEM8(0x0662)
2561#define PORTD_DIRTGL  _SFR_MEM8(0x0663)
2562#define PORTD_OUT  _SFR_MEM8(0x0664)
2563#define PORTD_OUTSET  _SFR_MEM8(0x0665)
2564#define PORTD_OUTCLR  _SFR_MEM8(0x0666)
2565#define PORTD_OUTTGL  _SFR_MEM8(0x0667)
2566#define PORTD_IN  _SFR_MEM8(0x0668)
2567#define PORTD_INTCTRL  _SFR_MEM8(0x0669)
2568#define PORTD_INT0MASK  _SFR_MEM8(0x066A)
2569#define PORTD_INT1MASK  _SFR_MEM8(0x066B)
2570#define PORTD_INTFLAGS  _SFR_MEM8(0x066C)
2571#define PORTD_PIN0CTRL  _SFR_MEM8(0x0670)
2572#define PORTD_PIN1CTRL  _SFR_MEM8(0x0671)
2573#define PORTD_PIN2CTRL  _SFR_MEM8(0x0672)
2574#define PORTD_PIN3CTRL  _SFR_MEM8(0x0673)
2575#define PORTD_PIN4CTRL  _SFR_MEM8(0x0674)
2576#define PORTD_PIN5CTRL  _SFR_MEM8(0x0675)
2577#define PORTD_PIN6CTRL  _SFR_MEM8(0x0676)
2578#define PORTD_PIN7CTRL  _SFR_MEM8(0x0677)
2579
2580/* PORTE - Port E */
2581#define PORTE_DIR  _SFR_MEM8(0x0680)
2582#define PORTE_DIRSET  _SFR_MEM8(0x0681)
2583#define PORTE_DIRCLR  _SFR_MEM8(0x0682)
2584#define PORTE_DIRTGL  _SFR_MEM8(0x0683)
2585#define PORTE_OUT  _SFR_MEM8(0x0684)
2586#define PORTE_OUTSET  _SFR_MEM8(0x0685)
2587#define PORTE_OUTCLR  _SFR_MEM8(0x0686)
2588#define PORTE_OUTTGL  _SFR_MEM8(0x0687)
2589#define PORTE_IN  _SFR_MEM8(0x0688)
2590#define PORTE_INTCTRL  _SFR_MEM8(0x0689)
2591#define PORTE_INT0MASK  _SFR_MEM8(0x068A)
2592#define PORTE_INT1MASK  _SFR_MEM8(0x068B)
2593#define PORTE_INTFLAGS  _SFR_MEM8(0x068C)
2594#define PORTE_PIN0CTRL  _SFR_MEM8(0x0690)
2595#define PORTE_PIN1CTRL  _SFR_MEM8(0x0691)
2596#define PORTE_PIN2CTRL  _SFR_MEM8(0x0692)
2597#define PORTE_PIN3CTRL  _SFR_MEM8(0x0693)
2598#define PORTE_PIN4CTRL  _SFR_MEM8(0x0694)
2599#define PORTE_PIN5CTRL  _SFR_MEM8(0x0695)
2600#define PORTE_PIN6CTRL  _SFR_MEM8(0x0696)
2601#define PORTE_PIN7CTRL  _SFR_MEM8(0x0697)
2602
2603/* PORTR - Port R */
2604#define PORTR_DIR  _SFR_MEM8(0x07E0)
2605#define PORTR_DIRSET  _SFR_MEM8(0x07E1)
2606#define PORTR_DIRCLR  _SFR_MEM8(0x07E2)
2607#define PORTR_DIRTGL  _SFR_MEM8(0x07E3)
2608#define PORTR_OUT  _SFR_MEM8(0x07E4)
2609#define PORTR_OUTSET  _SFR_MEM8(0x07E5)
2610#define PORTR_OUTCLR  _SFR_MEM8(0x07E6)
2611#define PORTR_OUTTGL  _SFR_MEM8(0x07E7)
2612#define PORTR_IN  _SFR_MEM8(0x07E8)
2613#define PORTR_INTCTRL  _SFR_MEM8(0x07E9)
2614#define PORTR_INT0MASK  _SFR_MEM8(0x07EA)
2615#define PORTR_INT1MASK  _SFR_MEM8(0x07EB)
2616#define PORTR_INTFLAGS  _SFR_MEM8(0x07EC)
2617#define PORTR_PIN0CTRL  _SFR_MEM8(0x07F0)
2618#define PORTR_PIN1CTRL  _SFR_MEM8(0x07F1)
2619#define PORTR_PIN2CTRL  _SFR_MEM8(0x07F2)
2620#define PORTR_PIN3CTRL  _SFR_MEM8(0x07F3)
2621#define PORTR_PIN4CTRL  _SFR_MEM8(0x07F4)
2622#define PORTR_PIN5CTRL  _SFR_MEM8(0x07F5)
2623#define PORTR_PIN6CTRL  _SFR_MEM8(0x07F6)
2624#define PORTR_PIN7CTRL  _SFR_MEM8(0x07F7)
2625
2626/* TCC0 - Timer/Counter C0 */
2627#define TCC0_CTRLA  _SFR_MEM8(0x0800)
2628#define TCC0_CTRLB  _SFR_MEM8(0x0801)
2629#define TCC0_CTRLC  _SFR_MEM8(0x0802)
2630#define TCC0_CTRLD  _SFR_MEM8(0x0803)
2631#define TCC0_CTRLE  _SFR_MEM8(0x0804)
2632#define TCC0_INTCTRLA  _SFR_MEM8(0x0806)
2633#define TCC0_INTCTRLB  _SFR_MEM8(0x0807)
2634#define TCC0_CTRLFCLR  _SFR_MEM8(0x0808)
2635#define TCC0_CTRLFSET  _SFR_MEM8(0x0809)
2636#define TCC0_CTRLGCLR  _SFR_MEM8(0x080A)
2637#define TCC0_CTRLGSET  _SFR_MEM8(0x080B)
2638#define TCC0_INTFLAGS  _SFR_MEM8(0x080C)
2639#define TCC0_TEMP  _SFR_MEM8(0x080F)
2640#define TCC0_CNT  _SFR_MEM16(0x0820)
2641#define TCC0_PER  _SFR_MEM16(0x0826)
2642#define TCC0_CCA  _SFR_MEM16(0x0828)
2643#define TCC0_CCB  _SFR_MEM16(0x082A)
2644#define TCC0_CCC  _SFR_MEM16(0x082C)
2645#define TCC0_CCD  _SFR_MEM16(0x082E)
2646#define TCC0_PERBUF  _SFR_MEM16(0x0836)
2647#define TCC0_CCABUF  _SFR_MEM16(0x0838)
2648#define TCC0_CCBBUF  _SFR_MEM16(0x083A)
2649#define TCC0_CCCBUF  _SFR_MEM16(0x083C)
2650#define TCC0_CCDBUF  _SFR_MEM16(0x083E)
2651
2652/* TCC1 - Timer/Counter C1 */
2653#define TCC1_CTRLA  _SFR_MEM8(0x0840)
2654#define TCC1_CTRLB  _SFR_MEM8(0x0841)
2655#define TCC1_CTRLC  _SFR_MEM8(0x0842)
2656#define TCC1_CTRLD  _SFR_MEM8(0x0843)
2657#define TCC1_CTRLE  _SFR_MEM8(0x0844)
2658#define TCC1_INTCTRLA  _SFR_MEM8(0x0846)
2659#define TCC1_INTCTRLB  _SFR_MEM8(0x0847)
2660#define TCC1_CTRLFCLR  _SFR_MEM8(0x0848)
2661#define TCC1_CTRLFSET  _SFR_MEM8(0x0849)
2662#define TCC1_CTRLGCLR  _SFR_MEM8(0x084A)
2663#define TCC1_CTRLGSET  _SFR_MEM8(0x084B)
2664#define TCC1_INTFLAGS  _SFR_MEM8(0x084C)
2665#define TCC1_TEMP  _SFR_MEM8(0x084F)
2666#define TCC1_CNT  _SFR_MEM16(0x0860)
2667#define TCC1_PER  _SFR_MEM16(0x0866)
2668#define TCC1_CCA  _SFR_MEM16(0x0868)
2669#define TCC1_CCB  _SFR_MEM16(0x086A)
2670#define TCC1_PERBUF  _SFR_MEM16(0x0876)
2671#define TCC1_CCABUF  _SFR_MEM16(0x0878)
2672#define TCC1_CCBBUF  _SFR_MEM16(0x087A)
2673
2674/* AWEXC - Advanced Waveform Extension C */
2675#define AWEXC_CTRL  _SFR_MEM8(0x0880)
2676#define AWEXC_FDEMASK  _SFR_MEM8(0x0882)
2677#define AWEXC_FDCTRL  _SFR_MEM8(0x0883)
2678#define AWEXC_STATUS  _SFR_MEM8(0x0884)
2679#define AWEXC_DTBOTH  _SFR_MEM8(0x0886)
2680#define AWEXC_DTBOTHBUF  _SFR_MEM8(0x0887)
2681#define AWEXC_DTLS  _SFR_MEM8(0x0888)
2682#define AWEXC_DTHS  _SFR_MEM8(0x0889)
2683#define AWEXC_DTLSBUF  _SFR_MEM8(0x088A)
2684#define AWEXC_DTHSBUF  _SFR_MEM8(0x088B)
2685#define AWEXC_OUTOVEN  _SFR_MEM8(0x088C)
2686
2687/* HIRESC - High-Resolution Extension C */
2688#define HIRESC_CTRLA  _SFR_MEM8(0x0890)
2689
2690/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
2691#define USARTC0_DATA  _SFR_MEM8(0x08A0)
2692#define USARTC0_STATUS  _SFR_MEM8(0x08A1)
2693#define USARTC0_CTRLA  _SFR_MEM8(0x08A3)
2694#define USARTC0_CTRLB  _SFR_MEM8(0x08A4)
2695#define USARTC0_CTRLC  _SFR_MEM8(0x08A5)
2696#define USARTC0_BAUDCTRLA  _SFR_MEM8(0x08A6)
2697#define USARTC0_BAUDCTRLB  _SFR_MEM8(0x08A7)
2698
2699/* SPIC - Serial Peripheral Interface C */
2700#define SPIC_CTRL  _SFR_MEM8(0x08C0)
2701#define SPIC_INTCTRL  _SFR_MEM8(0x08C1)
2702#define SPIC_STATUS  _SFR_MEM8(0x08C2)
2703#define SPIC_DATA  _SFR_MEM8(0x08C3)
2704
2705/* IRCOM - IR Communication Module */
2706#define IRCOM_CTRL  _SFR_MEM8(0x08F8)
2707#define IRCOM_TXPLCTRL  _SFR_MEM8(0x08F9)
2708#define IRCOM_RXPLCTRL  _SFR_MEM8(0x08FA)
2709
2710/* TCD0 - Timer/Counter D0 */
2711#define TCD0_CTRLA  _SFR_MEM8(0x0900)
2712#define TCD0_CTRLB  _SFR_MEM8(0x0901)
2713#define TCD0_CTRLC  _SFR_MEM8(0x0902)
2714#define TCD0_CTRLD  _SFR_MEM8(0x0903)
2715#define TCD0_CTRLE  _SFR_MEM8(0x0904)
2716#define TCD0_INTCTRLA  _SFR_MEM8(0x0906)
2717#define TCD0_INTCTRLB  _SFR_MEM8(0x0907)
2718#define TCD0_CTRLFCLR  _SFR_MEM8(0x0908)
2719#define TCD0_CTRLFSET  _SFR_MEM8(0x0909)
2720#define TCD0_CTRLGCLR  _SFR_MEM8(0x090A)
2721#define TCD0_CTRLGSET  _SFR_MEM8(0x090B)
2722#define TCD0_INTFLAGS  _SFR_MEM8(0x090C)
2723#define TCD0_TEMP  _SFR_MEM8(0x090F)
2724#define TCD0_CNT  _SFR_MEM16(0x0920)
2725#define TCD0_PER  _SFR_MEM16(0x0926)
2726#define TCD0_CCA  _SFR_MEM16(0x0928)
2727#define TCD0_CCB  _SFR_MEM16(0x092A)
2728#define TCD0_CCC  _SFR_MEM16(0x092C)
2729#define TCD0_CCD  _SFR_MEM16(0x092E)
2730#define TCD0_PERBUF  _SFR_MEM16(0x0936)
2731#define TCD0_CCABUF  _SFR_MEM16(0x0938)
2732#define TCD0_CCBBUF  _SFR_MEM16(0x093A)
2733#define TCD0_CCCBUF  _SFR_MEM16(0x093C)
2734#define TCD0_CCDBUF  _SFR_MEM16(0x093E)
2735
2736/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
2737#define USARTD0_DATA  _SFR_MEM8(0x09A0)
2738#define USARTD0_STATUS  _SFR_MEM8(0x09A1)
2739#define USARTD0_CTRLA  _SFR_MEM8(0x09A3)
2740#define USARTD0_CTRLB  _SFR_MEM8(0x09A4)
2741#define USARTD0_CTRLC  _SFR_MEM8(0x09A5)
2742#define USARTD0_BAUDCTRLA  _SFR_MEM8(0x09A6)
2743#define USARTD0_BAUDCTRLB  _SFR_MEM8(0x09A7)
2744
2745/* SPID - Serial Peripheral Interface D */
2746#define SPID_CTRL  _SFR_MEM8(0x09C0)
2747#define SPID_INTCTRL  _SFR_MEM8(0x09C1)
2748#define SPID_STATUS  _SFR_MEM8(0x09C2)
2749#define SPID_DATA  _SFR_MEM8(0x09C3)
2750
2751/* TCE0 - Timer/Counter E0 */
2752#define TCE0_CTRLA  _SFR_MEM8(0x0A00)
2753#define TCE0_CTRLB  _SFR_MEM8(0x0A01)
2754#define TCE0_CTRLC  _SFR_MEM8(0x0A02)
2755#define TCE0_CTRLD  _SFR_MEM8(0x0A03)
2756#define TCE0_CTRLE  _SFR_MEM8(0x0A04)
2757#define TCE0_INTCTRLA  _SFR_MEM8(0x0A06)
2758#define TCE0_INTCTRLB  _SFR_MEM8(0x0A07)
2759#define TCE0_CTRLFCLR  _SFR_MEM8(0x0A08)
2760#define TCE0_CTRLFSET  _SFR_MEM8(0x0A09)
2761#define TCE0_CTRLGCLR  _SFR_MEM8(0x0A0A)
2762#define TCE0_CTRLGSET  _SFR_MEM8(0x0A0B)
2763#define TCE0_INTFLAGS  _SFR_MEM8(0x0A0C)
2764#define TCE0_TEMP  _SFR_MEM8(0x0A0F)
2765#define TCE0_CNT  _SFR_MEM16(0x0A20)
2766#define TCE0_PER  _SFR_MEM16(0x0A26)
2767#define TCE0_CCA  _SFR_MEM16(0x0A28)
2768#define TCE0_CCB  _SFR_MEM16(0x0A2A)
2769#define TCE0_CCC  _SFR_MEM16(0x0A2C)
2770#define TCE0_CCD  _SFR_MEM16(0x0A2E)
2771#define TCE0_PERBUF  _SFR_MEM16(0x0A36)
2772#define TCE0_CCABUF  _SFR_MEM16(0x0A38)
2773#define TCE0_CCBBUF  _SFR_MEM16(0x0A3A)
2774#define TCE0_CCCBUF  _SFR_MEM16(0x0A3C)
2775#define TCE0_CCDBUF  _SFR_MEM16(0x0A3E)
2776
2777
2778
2779/*================== Bitfield Definitions ================== */
2780
2781/* XOCD - On-Chip Debug System */
2782/* OCD.OCDR1  bit masks and bit positions */
2783#define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
2784#define OCD_OCDRD_bp  0  /* OCDR Dirty bit position. */
2785
2786
2787/* CPU - CPU */
2788/* CPU.CCP  bit masks and bit positions */
2789#define CPU_CCP_gm  0xFF  /* CCP signature group mask. */
2790#define CPU_CCP_gp  0  /* CCP signature group position. */
2791#define CPU_CCP0_bm  (1<<0)  /* CCP signature bit 0 mask. */
2792#define CPU_CCP0_bp  0  /* CCP signature bit 0 position. */
2793#define CPU_CCP1_bm  (1<<1)  /* CCP signature bit 1 mask. */
2794#define CPU_CCP1_bp  1  /* CCP signature bit 1 position. */
2795#define CPU_CCP2_bm  (1<<2)  /* CCP signature bit 2 mask. */
2796#define CPU_CCP2_bp  2  /* CCP signature bit 2 position. */
2797#define CPU_CCP3_bm  (1<<3)  /* CCP signature bit 3 mask. */
2798#define CPU_CCP3_bp  3  /* CCP signature bit 3 position. */
2799#define CPU_CCP4_bm  (1<<4)  /* CCP signature bit 4 mask. */
2800#define CPU_CCP4_bp  4  /* CCP signature bit 4 position. */
2801#define CPU_CCP5_bm  (1<<5)  /* CCP signature bit 5 mask. */
2802#define CPU_CCP5_bp  5  /* CCP signature bit 5 position. */
2803#define CPU_CCP6_bm  (1<<6)  /* CCP signature bit 6 mask. */
2804#define CPU_CCP6_bp  6  /* CCP signature bit 6 position. */
2805#define CPU_CCP7_bm  (1<<7)  /* CCP signature bit 7 mask. */
2806#define CPU_CCP7_bp  7  /* CCP signature bit 7 position. */
2807
2808
2809/* CPU.SREG  bit masks and bit positions */
2810#define CPU_I_bm  0x80  /* Global Interrupt Enable Flag bit mask. */
2811#define CPU_I_bp  7  /* Global Interrupt Enable Flag bit position. */
2812
2813#define CPU_T_bm  0x40  /* Transfer Bit bit mask. */
2814#define CPU_T_bp  6  /* Transfer Bit bit position. */
2815
2816#define CPU_H_bm  0x20  /* Half Carry Flag bit mask. */
2817#define CPU_H_bp  5  /* Half Carry Flag bit position. */
2818
2819#define CPU_S_bm  0x10  /* N Exclusive Or V Flag bit mask. */
2820#define CPU_S_bp  4  /* N Exclusive Or V Flag bit position. */
2821
2822#define CPU_V_bm  0x08  /* Two's Complement Overflow Flag bit mask. */
2823#define CPU_V_bp  3  /* Two's Complement Overflow Flag bit position. */
2824
2825#define CPU_N_bm  0x04  /* Negative Flag bit mask. */
2826#define CPU_N_bp  2  /* Negative Flag bit position. */
2827
2828#define CPU_Z_bm  0x02  /* Zero Flag bit mask. */
2829#define CPU_Z_bp  1  /* Zero Flag bit position. */
2830
2831#define CPU_C_bm  0x01  /* Carry Flag bit mask. */
2832#define CPU_C_bp  0  /* Carry Flag bit position. */
2833
2834
2835/* CLK - Clock System */
2836/* CLK.CTRL  bit masks and bit positions */
2837#define CLK_SCLKSEL_gm  0x07  /* System Clock Selection group mask. */
2838#define CLK_SCLKSEL_gp  0  /* System Clock Selection group position. */
2839#define CLK_SCLKSEL0_bm  (1<<0)  /* System Clock Selection bit 0 mask. */
2840#define CLK_SCLKSEL0_bp  0  /* System Clock Selection bit 0 position. */
2841#define CLK_SCLKSEL1_bm  (1<<1)  /* System Clock Selection bit 1 mask. */
2842#define CLK_SCLKSEL1_bp  1  /* System Clock Selection bit 1 position. */
2843#define CLK_SCLKSEL2_bm  (1<<2)  /* System Clock Selection bit 2 mask. */
2844#define CLK_SCLKSEL2_bp  2  /* System Clock Selection bit 2 position. */
2845
2846
2847/* CLK.PSCTRL  bit masks and bit positions */
2848#define CLK_PSADIV_gm  0x7C  /* Prescaler A Division Factor group mask. */
2849#define CLK_PSADIV_gp  2  /* Prescaler A Division Factor group position. */
2850#define CLK_PSADIV0_bm  (1<<2)  /* Prescaler A Division Factor bit 0 mask. */
2851#define CLK_PSADIV0_bp  2  /* Prescaler A Division Factor bit 0 position. */
2852#define CLK_PSADIV1_bm  (1<<3)  /* Prescaler A Division Factor bit 1 mask. */
2853#define CLK_PSADIV1_bp  3  /* Prescaler A Division Factor bit 1 position. */
2854#define CLK_PSADIV2_bm  (1<<4)  /* Prescaler A Division Factor bit 2 mask. */
2855#define CLK_PSADIV2_bp  4  /* Prescaler A Division Factor bit 2 position. */
2856#define CLK_PSADIV3_bm  (1<<5)  /* Prescaler A Division Factor bit 3 mask. */
2857#define CLK_PSADIV3_bp  5  /* Prescaler A Division Factor bit 3 position. */
2858#define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
2859#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
2860
2861#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
2862#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
2863#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
2864#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
2865#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
2866#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
2867
2868
2869/* CLK.LOCK  bit masks and bit positions */
2870#define CLK_LOCK_bm  0x01  /* Clock System Lock bit mask. */
2871#define CLK_LOCK_bp  0  /* Clock System Lock bit position. */
2872
2873
2874/* CLK.RTCCTRL  bit masks and bit positions */
2875#define CLK_RTCSRC_gm  0x0E  /* Clock Source group mask. */
2876#define CLK_RTCSRC_gp  1  /* Clock Source group position. */
2877#define CLK_RTCSRC0_bm  (1<<1)  /* Clock Source bit 0 mask. */
2878#define CLK_RTCSRC0_bp  1  /* Clock Source bit 0 position. */
2879#define CLK_RTCSRC1_bm  (1<<2)  /* Clock Source bit 1 mask. */
2880#define CLK_RTCSRC1_bp  2  /* Clock Source bit 1 position. */
2881#define CLK_RTCSRC2_bm  (1<<3)  /* Clock Source bit 2 mask. */
2882#define CLK_RTCSRC2_bp  3  /* Clock Source bit 2 position. */
2883
2884#define CLK_RTCEN_bm  0x01  /* RTC Clock Source Enable bit mask. */
2885#define CLK_RTCEN_bp  0  /* RTC Clock Source Enable bit position. */
2886
2887
2888/* PR.PRGEN  bit masks and bit positions */
2889#define PR_AES_bm  0x10  /* AES bit mask. */
2890#define PR_AES_bp  4  /* AES bit position. */
2891
2892#define PR_EBI_bm  0x08  /* External Bus Interface bit mask. */
2893#define PR_EBI_bp  3  /* External Bus Interface bit position. */
2894
2895#define PR_RTC_bm  0x04  /* Real-time Counter bit mask. */
2896#define PR_RTC_bp  2  /* Real-time Counter bit position. */
2897
2898#define PR_EVSYS_bm  0x02  /* Event System bit mask. */
2899#define PR_EVSYS_bp  1  /* Event System bit position. */
2900
2901#define PR_DMA_bm  0x01  /* DMA-Controller bit mask. */
2902#define PR_DMA_bp  0  /* DMA-Controller bit position. */
2903
2904
2905/* PR.PRPA  bit masks and bit positions */
2906#define PR_DAC_bm  0x04  /* Port A DAC bit mask. */
2907#define PR_DAC_bp  2  /* Port A DAC bit position. */
2908
2909#define PR_ADC_bm  0x02  /* Port A ADC bit mask. */
2910#define PR_ADC_bp  1  /* Port A ADC bit position. */
2911
2912#define PR_AC_bm  0x01  /* Port A Analog Comparator bit mask. */
2913#define PR_AC_bp  0  /* Port A Analog Comparator bit position. */
2914
2915
2916/* PR.PRPB  bit masks and bit positions */
2917/* PR_DAC_bm  Predefined. */
2918/* PR_DAC_bp  Predefined. */
2919
2920/* PR_ADC_bm  Predefined. */
2921/* PR_ADC_bp  Predefined. */
2922
2923/* PR_AC_bm  Predefined. */
2924/* PR_AC_bp  Predefined. */
2925
2926
2927/* PR.PRPC  bit masks and bit positions */
2928#define PR_TWI_bm  0x40  /* Port C Two-wire Interface bit mask. */
2929#define PR_TWI_bp  6  /* Port C Two-wire Interface bit position. */
2930
2931#define PR_USART1_bm  0x20  /* Port C USART1 bit mask. */
2932#define PR_USART1_bp  5  /* Port C USART1 bit position. */
2933
2934#define PR_USART0_bm  0x10  /* Port C USART0 bit mask. */
2935#define PR_USART0_bp  4  /* Port C USART0 bit position. */
2936
2937#define PR_SPI_bm  0x08  /* Port C SPI bit mask. */
2938#define PR_SPI_bp  3  /* Port C SPI bit position. */
2939
2940#define PR_HIRES_bm  0x04  /* Port C AWEX bit mask. */
2941#define PR_HIRES_bp  2  /* Port C AWEX bit position. */
2942
2943#define PR_TC1_bm  0x02  /* Port C Timer/Counter1 bit mask. */
2944#define PR_TC1_bp  1  /* Port C Timer/Counter1 bit position. */
2945
2946#define PR_TC0_bm  0x01  /* Port C Timer/Counter0 bit mask. */
2947#define PR_TC0_bp  0  /* Port C Timer/Counter0 bit position. */
2948
2949
2950/* PR.PRPD  bit masks and bit positions */
2951/* PR_TWI_bm  Predefined. */
2952/* PR_TWI_bp  Predefined. */
2953
2954/* PR_USART1_bm  Predefined. */
2955/* PR_USART1_bp  Predefined. */
2956
2957/* PR_USART0_bm  Predefined. */
2958/* PR_USART0_bp  Predefined. */
2959
2960/* PR_SPI_bm  Predefined. */
2961/* PR_SPI_bp  Predefined. */
2962
2963/* PR_HIRES_bm  Predefined. */
2964/* PR_HIRES_bp  Predefined. */
2965
2966/* PR_TC1_bm  Predefined. */
2967/* PR_TC1_bp  Predefined. */
2968
2969/* PR_TC0_bm  Predefined. */
2970/* PR_TC0_bp  Predefined. */
2971
2972
2973/* PR.PRPE  bit masks and bit positions */
2974/* PR_TWI_bm  Predefined. */
2975/* PR_TWI_bp  Predefined. */
2976
2977/* PR_USART1_bm  Predefined. */
2978/* PR_USART1_bp  Predefined. */
2979
2980/* PR_USART0_bm  Predefined. */
2981/* PR_USART0_bp  Predefined. */
2982
2983/* PR_SPI_bm  Predefined. */
2984/* PR_SPI_bp  Predefined. */
2985
2986/* PR_HIRES_bm  Predefined. */
2987/* PR_HIRES_bp  Predefined. */
2988
2989/* PR_TC1_bm  Predefined. */
2990/* PR_TC1_bp  Predefined. */
2991
2992/* PR_TC0_bm  Predefined. */
2993/* PR_TC0_bp  Predefined. */
2994
2995
2996/* PR.PRPF  bit masks and bit positions */
2997/* PR_TWI_bm  Predefined. */
2998/* PR_TWI_bp  Predefined. */
2999
3000/* PR_USART1_bm  Predefined. */
3001/* PR_USART1_bp  Predefined. */
3002
3003/* PR_USART0_bm  Predefined. */
3004/* PR_USART0_bp  Predefined. */
3005
3006/* PR_SPI_bm  Predefined. */
3007/* PR_SPI_bp  Predefined. */
3008
3009/* PR_HIRES_bm  Predefined. */
3010/* PR_HIRES_bp  Predefined. */
3011
3012/* PR_TC1_bm  Predefined. */
3013/* PR_TC1_bp  Predefined. */
3014
3015/* PR_TC0_bm  Predefined. */
3016/* PR_TC0_bp  Predefined. */
3017
3018
3019/* SLEEP - Sleep Controller */
3020/* SLEEP.CTRL  bit masks and bit positions */
3021#define SLEEP_SMODE_gm  0x0E  /* Sleep Mode group mask. */
3022#define SLEEP_SMODE_gp  1  /* Sleep Mode group position. */
3023#define SLEEP_SMODE0_bm  (1<<1)  /* Sleep Mode bit 0 mask. */
3024#define SLEEP_SMODE0_bp  1  /* Sleep Mode bit 0 position. */
3025#define SLEEP_SMODE1_bm  (1<<2)  /* Sleep Mode bit 1 mask. */
3026#define SLEEP_SMODE1_bp  2  /* Sleep Mode bit 1 position. */
3027#define SLEEP_SMODE2_bm  (1<<3)  /* Sleep Mode bit 2 mask. */
3028#define SLEEP_SMODE2_bp  3  /* Sleep Mode bit 2 position. */
3029
3030#define SLEEP_SEN_bm  0x01  /* Sleep Enable bit mask. */
3031#define SLEEP_SEN_bp  0  /* Sleep Enable bit position. */
3032
3033
3034/* OSC - Oscillator */
3035/* OSC.CTRL  bit masks and bit positions */
3036#define OSC_PLLEN_bm  0x10  /* PLL Enable bit mask. */
3037#define OSC_PLLEN_bp  4  /* PLL Enable bit position. */
3038
3039#define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
3040#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
3041
3042#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
3043#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
3044
3045#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
3046#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
3047
3048#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
3049#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
3050
3051
3052/* OSC.STATUS  bit masks and bit positions */
3053#define OSC_PLLRDY_bm  0x10  /* PLL Ready bit mask. */
3054#define OSC_PLLRDY_bp  4  /* PLL Ready bit position. */
3055
3056#define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
3057#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
3058
3059#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
3060#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
3061
3062#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
3063#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
3064
3065#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
3066#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
3067
3068
3069/* OSC.XOSCCTRL  bit masks and bit positions */
3070#define OSC_FRQRANGE_gm  0xC0  /* Frequency Range group mask. */
3071#define OSC_FRQRANGE_gp  6  /* Frequency Range group position. */
3072#define OSC_FRQRANGE0_bm  (1<<6)  /* Frequency Range bit 0 mask. */
3073#define OSC_FRQRANGE0_bp  6  /* Frequency Range bit 0 position. */
3074#define OSC_FRQRANGE1_bm  (1<<7)  /* Frequency Range bit 1 mask. */
3075#define OSC_FRQRANGE1_bp  7  /* Frequency Range bit 1 position. */
3076
3077#define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
3078#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
3079
3080#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
3081#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
3082#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
3083#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
3084#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
3085#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
3086#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
3087#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
3088#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
3089#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
3090
3091
3092/* OSC.XOSCFAIL  bit masks and bit positions */
3093#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
3094#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
3095
3096#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
3097#define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
3098
3099
3100/* OSC.PLLCTRL  bit masks and bit positions */
3101#define OSC_PLLSRC_gm  0xC0  /* Clock Source group mask. */
3102#define OSC_PLLSRC_gp  6  /* Clock Source group position. */
3103#define OSC_PLLSRC0_bm  (1<<6)  /* Clock Source bit 0 mask. */
3104#define OSC_PLLSRC0_bp  6  /* Clock Source bit 0 position. */
3105#define OSC_PLLSRC1_bm  (1<<7)  /* Clock Source bit 1 mask. */
3106#define OSC_PLLSRC1_bp  7  /* Clock Source bit 1 position. */
3107
3108#define OSC_PLLFAC_gm  0x1F  /* Multiplication Factor group mask. */
3109#define OSC_PLLFAC_gp  0  /* Multiplication Factor group position. */
3110#define OSC_PLLFAC0_bm  (1<<0)  /* Multiplication Factor bit 0 mask. */
3111#define OSC_PLLFAC0_bp  0  /* Multiplication Factor bit 0 position. */
3112#define OSC_PLLFAC1_bm  (1<<1)  /* Multiplication Factor bit 1 mask. */
3113#define OSC_PLLFAC1_bp  1  /* Multiplication Factor bit 1 position. */
3114#define OSC_PLLFAC2_bm  (1<<2)  /* Multiplication Factor bit 2 mask. */
3115#define OSC_PLLFAC2_bp  2  /* Multiplication Factor bit 2 position. */
3116#define OSC_PLLFAC3_bm  (1<<3)  /* Multiplication Factor bit 3 mask. */
3117#define OSC_PLLFAC3_bp  3  /* Multiplication Factor bit 3 position. */
3118#define OSC_PLLFAC4_bm  (1<<4)  /* Multiplication Factor bit 4 mask. */
3119#define OSC_PLLFAC4_bp  4  /* Multiplication Factor bit 4 position. */
3120
3121
3122/* OSC.DFLLCTRL  bit masks and bit positions */
3123#define OSC_RC32MCREF_bm  0x02  /* 32MHz Calibration Reference bit mask. */
3124#define OSC_RC32MCREF_bp  1  /* 32MHz Calibration Reference bit position. */
3125
3126#define OSC_RC2MCREF_bm  0x01  /* 2MHz Calibration Reference bit mask. */
3127#define OSC_RC2MCREF_bp  0  /* 2MHz Calibration Reference bit position. */
3128
3129
3130/* DFLL - DFLL */
3131/* DFLL.CTRL  bit masks and bit positions */
3132#define DFLL_ENABLE_bm  0x01  /* DFLL Enable bit mask. */
3133#define DFLL_ENABLE_bp  0  /* DFLL Enable bit position. */
3134
3135
3136/* DFLL.CALA  bit masks and bit positions */
3137#define DFLL_CALL_gm  0x7F  /* DFLL Calibration bits [6:0] group mask. */
3138#define DFLL_CALL_gp  0  /* DFLL Calibration bits [6:0] group position. */
3139#define DFLL_CALL0_bm  (1<<0)  /* DFLL Calibration bits [6:0] bit 0 mask. */
3140#define DFLL_CALL0_bp  0  /* DFLL Calibration bits [6:0] bit 0 position. */
3141#define DFLL_CALL1_bm  (1<<1)  /* DFLL Calibration bits [6:0] bit 1 mask. */
3142#define DFLL_CALL1_bp  1  /* DFLL Calibration bits [6:0] bit 1 position. */
3143#define DFLL_CALL2_bm  (1<<2)  /* DFLL Calibration bits [6:0] bit 2 mask. */
3144#define DFLL_CALL2_bp  2  /* DFLL Calibration bits [6:0] bit 2 position. */
3145#define DFLL_CALL3_bm  (1<<3)  /* DFLL Calibration bits [6:0] bit 3 mask. */
3146#define DFLL_CALL3_bp  3  /* DFLL Calibration bits [6:0] bit 3 position. */
3147#define DFLL_CALL4_bm  (1<<4)  /* DFLL Calibration bits [6:0] bit 4 mask. */
3148#define DFLL_CALL4_bp  4  /* DFLL Calibration bits [6:0] bit 4 position. */
3149#define DFLL_CALL5_bm  (1<<5)  /* DFLL Calibration bits [6:0] bit 5 mask. */
3150#define DFLL_CALL5_bp  5  /* DFLL Calibration bits [6:0] bit 5 position. */
3151#define DFLL_CALL6_bm  (1<<6)  /* DFLL Calibration bits [6:0] bit 6 mask. */
3152#define DFLL_CALL6_bp  6  /* DFLL Calibration bits [6:0] bit 6 position. */
3153
3154
3155/* DFLL.CALB  bit masks and bit positions */
3156#define DFLL_CALH_gm  0x3F  /* DFLL Calibration bits [12:7] group mask. */
3157#define DFLL_CALH_gp  0  /* DFLL Calibration bits [12:7] group position. */
3158#define DFLL_CALH0_bm  (1<<0)  /* DFLL Calibration bits [12:7] bit 0 mask. */
3159#define DFLL_CALH0_bp  0  /* DFLL Calibration bits [12:7] bit 0 position. */
3160#define DFLL_CALH1_bm  (1<<1)  /* DFLL Calibration bits [12:7] bit 1 mask. */
3161#define DFLL_CALH1_bp  1  /* DFLL Calibration bits [12:7] bit 1 position. */
3162#define DFLL_CALH2_bm  (1<<2)  /* DFLL Calibration bits [12:7] bit 2 mask. */
3163#define DFLL_CALH2_bp  2  /* DFLL Calibration bits [12:7] bit 2 position. */
3164#define DFLL_CALH3_bm  (1<<3)  /* DFLL Calibration bits [12:7] bit 3 mask. */
3165#define DFLL_CALH3_bp  3  /* DFLL Calibration bits [12:7] bit 3 position. */
3166#define DFLL_CALH4_bm  (1<<4)  /* DFLL Calibration bits [12:7] bit 4 mask. */
3167#define DFLL_CALH4_bp  4  /* DFLL Calibration bits [12:7] bit 4 position. */
3168#define DFLL_CALH5_bm  (1<<5)  /* DFLL Calibration bits [12:7] bit 5 mask. */
3169#define DFLL_CALH5_bp  5  /* DFLL Calibration bits [12:7] bit 5 position. */
3170
3171
3172/* RST - Reset */
3173/* RST.STATUS  bit masks and bit positions */
3174#define RST_SDRF_bm  0x40  /* Spike Detection Reset Flag bit mask. */
3175#define RST_SDRF_bp  6  /* Spike Detection Reset Flag bit position. */
3176
3177#define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
3178#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
3179
3180#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
3181#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
3182
3183#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
3184#define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
3185
3186#define RST_BORF_bm  0x04  /* Brown-out Reset Flag bit mask. */
3187#define RST_BORF_bp  2  /* Brown-out Reset Flag bit position. */
3188
3189#define RST_EXTRF_bm  0x02  /* External Reset Flag bit mask. */
3190#define RST_EXTRF_bp  1  /* External Reset Flag bit position. */
3191
3192#define RST_PORF_bm  0x01  /* Power-on Reset Flag bit mask. */
3193#define RST_PORF_bp  0  /* Power-on Reset Flag bit position. */
3194
3195
3196/* RST.CTRL  bit masks and bit positions */
3197#define RST_SWRST_bm  0x01  /* Software Reset bit mask. */
3198#define RST_SWRST_bp  0  /* Software Reset bit position. */
3199
3200
3201/* WDT - Watch-Dog Timer */
3202/* WDT.CTRL  bit masks and bit positions */
3203#define WDT_PER_gm  0x3C  /* Period group mask. */
3204#define WDT_PER_gp  2  /* Period group position. */
3205#define WDT_PER0_bm  (1<<2)  /* Period bit 0 mask. */
3206#define WDT_PER0_bp  2  /* Period bit 0 position. */
3207#define WDT_PER1_bm  (1<<3)  /* Period bit 1 mask. */
3208#define WDT_PER1_bp  3  /* Period bit 1 position. */
3209#define WDT_PER2_bm  (1<<4)  /* Period bit 2 mask. */
3210#define WDT_PER2_bp  4  /* Period bit 2 position. */
3211#define WDT_PER3_bm  (1<<5)  /* Period bit 3 mask. */
3212#define WDT_PER3_bp  5  /* Period bit 3 position. */
3213
3214#define WDT_ENABLE_bm  0x02  /* Enable bit mask. */
3215#define WDT_ENABLE_bp  1  /* Enable bit position. */
3216
3217#define WDT_CEN_bm  0x01  /* Change Enable bit mask. */
3218#define WDT_CEN_bp  0  /* Change Enable bit position. */
3219
3220
3221/* WDT.WINCTRL  bit masks and bit positions */
3222#define WDT_WPER_gm  0x3C  /* Windowed Mode Period group mask. */
3223#define WDT_WPER_gp  2  /* Windowed Mode Period group position. */
3224#define WDT_WPER0_bm  (1<<2)  /* Windowed Mode Period bit 0 mask. */
3225#define WDT_WPER0_bp  2  /* Windowed Mode Period bit 0 position. */
3226#define WDT_WPER1_bm  (1<<3)  /* Windowed Mode Period bit 1 mask. */
3227#define WDT_WPER1_bp  3  /* Windowed Mode Period bit 1 position. */
3228#define WDT_WPER2_bm  (1<<4)  /* Windowed Mode Period bit 2 mask. */
3229#define WDT_WPER2_bp  4  /* Windowed Mode Period bit 2 position. */
3230#define WDT_WPER3_bm  (1<<5)  /* Windowed Mode Period bit 3 mask. */
3231#define WDT_WPER3_bp  5  /* Windowed Mode Period bit 3 position. */
3232
3233#define WDT_WEN_bm  0x02  /* Windowed Mode Enable bit mask. */
3234#define WDT_WEN_bp  1  /* Windowed Mode Enable bit position. */
3235
3236#define WDT_WCEN_bm  0x01  /* Windowed Mode Change Enable bit mask. */
3237#define WDT_WCEN_bp  0  /* Windowed Mode Change Enable bit position. */
3238
3239
3240/* WDT.STATUS  bit masks and bit positions */
3241#define WDT_SYNCBUSY_bm  0x01  /* Syncronization busy bit mask. */
3242#define WDT_SYNCBUSY_bp  0  /* Syncronization busy bit position. */
3243
3244
3245/* MCU - MCU Control */
3246/* MCU.MCUCR  bit masks and bit positions */
3247#define MCU_JTAGD_bm  0x01  /* JTAG Disable bit mask. */
3248#define MCU_JTAGD_bp  0  /* JTAG Disable bit position. */
3249
3250
3251/* MCU.EVSYSLOCK  bit masks and bit positions */
3252#define MCU_EVSYS1LOCK_bm  0x10  /* Event Channel 4-7 Lock bit mask. */
3253#define MCU_EVSYS1LOCK_bp  4  /* Event Channel 4-7 Lock bit position. */
3254
3255#define MCU_EVSYS0LOCK_bm  0x01  /* Event Channel 0-3 Lock bit mask. */
3256#define MCU_EVSYS0LOCK_bp  0  /* Event Channel 0-3 Lock bit position. */
3257
3258
3259/* MCU.AWEXLOCK  bit masks and bit positions */
3260#define MCU_AWEXELOCK_bm  0x04  /* AWeX on T/C E0 Lock bit mask. */
3261#define MCU_AWEXELOCK_bp  2  /* AWeX on T/C E0 Lock bit position. */
3262
3263#define MCU_AWEXCLOCK_bm  0x01  /* AWeX on T/C C0 Lock bit mask. */
3264#define MCU_AWEXCLOCK_bp  0  /* AWeX on T/C C0 Lock bit position. */
3265
3266
3267/* PMIC - Programmable Multi-level Interrupt Controller */
3268/* PMIC.STATUS  bit masks and bit positions */
3269#define PMIC_NMIEX_bm  0x80  /* Non-maskable Interrupt Executing bit mask. */
3270#define PMIC_NMIEX_bp  7  /* Non-maskable Interrupt Executing bit position. */
3271
3272#define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
3273#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
3274
3275#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
3276#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
3277
3278#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
3279#define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
3280
3281
3282/* PMIC.CTRL  bit masks and bit positions */
3283#define PMIC_RREN_bm  0x80  /* Round-Robin Priority Enable bit mask. */
3284#define PMIC_RREN_bp  7  /* Round-Robin Priority Enable bit position. */
3285
3286#define PMIC_IVSEL_bm  0x40  /* Interrupt Vector Select bit mask. */
3287#define PMIC_IVSEL_bp  6  /* Interrupt Vector Select bit position. */
3288
3289#define PMIC_HILVLEN_bm  0x04  /* High Level Enable bit mask. */
3290#define PMIC_HILVLEN_bp  2  /* High Level Enable bit position. */
3291
3292#define PMIC_MEDLVLEN_bm  0x02  /* Medium Level Enable bit mask. */
3293#define PMIC_MEDLVLEN_bp  1  /* Medium Level Enable bit position. */
3294
3295#define PMIC_LOLVLEN_bm  0x01  /* Low Level Enable bit mask. */
3296#define PMIC_LOLVLEN_bp  0  /* Low Level Enable bit position. */
3297
3298
3299/* EVSYS - Event System */
3300/* EVSYS.CH0MUX  bit masks and bit positions */
3301#define EVSYS_CHMUX_gm  0xFF  /* Event Channel 0 Multiplexer group mask. */
3302#define EVSYS_CHMUX_gp  0  /* Event Channel 0 Multiplexer group position. */
3303#define EVSYS_CHMUX0_bm  (1<<0)  /* Event Channel 0 Multiplexer bit 0 mask. */
3304#define EVSYS_CHMUX0_bp  0  /* Event Channel 0 Multiplexer bit 0 position. */
3305#define EVSYS_CHMUX1_bm  (1<<1)  /* Event Channel 0 Multiplexer bit 1 mask. */
3306#define EVSYS_CHMUX1_bp  1  /* Event Channel 0 Multiplexer bit 1 position. */
3307#define EVSYS_CHMUX2_bm  (1<<2)  /* Event Channel 0 Multiplexer bit 2 mask. */
3308#define EVSYS_CHMUX2_bp  2  /* Event Channel 0 Multiplexer bit 2 position. */
3309#define EVSYS_CHMUX3_bm  (1<<3)  /* Event Channel 0 Multiplexer bit 3 mask. */
3310#define EVSYS_CHMUX3_bp  3  /* Event Channel 0 Multiplexer bit 3 position. */
3311#define EVSYS_CHMUX4_bm  (1<<4)  /* Event Channel 0 Multiplexer bit 4 mask. */
3312#define EVSYS_CHMUX4_bp  4  /* Event Channel 0 Multiplexer bit 4 position. */
3313#define EVSYS_CHMUX5_bm  (1<<5)  /* Event Channel 0 Multiplexer bit 5 mask. */
3314#define EVSYS_CHMUX5_bp  5  /* Event Channel 0 Multiplexer bit 5 position. */
3315#define EVSYS_CHMUX6_bm  (1<<6)  /* Event Channel 0 Multiplexer bit 6 mask. */
3316#define EVSYS_CHMUX6_bp  6  /* Event Channel 0 Multiplexer bit 6 position. */
3317#define EVSYS_CHMUX7_bm  (1<<7)  /* Event Channel 0 Multiplexer bit 7 mask. */
3318#define EVSYS_CHMUX7_bp  7  /* Event Channel 0 Multiplexer bit 7 position. */
3319
3320
3321/* EVSYS.CH1MUX  bit masks and bit positions */
3322/* EVSYS_CHMUX_gm  Predefined. */
3323/* EVSYS_CHMUX_gp  Predefined. */
3324/* EVSYS_CHMUX0_bm  Predefined. */
3325/* EVSYS_CHMUX0_bp  Predefined. */
3326/* EVSYS_CHMUX1_bm  Predefined. */
3327/* EVSYS_CHMUX1_bp  Predefined. */
3328/* EVSYS_CHMUX2_bm  Predefined. */
3329/* EVSYS_CHMUX2_bp  Predefined. */
3330/* EVSYS_CHMUX3_bm  Predefined. */
3331/* EVSYS_CHMUX3_bp  Predefined. */
3332/* EVSYS_CHMUX4_bm  Predefined. */
3333/* EVSYS_CHMUX4_bp  Predefined. */
3334/* EVSYS_CHMUX5_bm  Predefined. */
3335/* EVSYS_CHMUX5_bp  Predefined. */
3336/* EVSYS_CHMUX6_bm  Predefined. */
3337/* EVSYS_CHMUX6_bp  Predefined. */
3338/* EVSYS_CHMUX7_bm  Predefined. */
3339/* EVSYS_CHMUX7_bp  Predefined. */
3340
3341
3342/* EVSYS.CH2MUX  bit masks and bit positions */
3343/* EVSYS_CHMUX_gm  Predefined. */
3344/* EVSYS_CHMUX_gp  Predefined. */
3345/* EVSYS_CHMUX0_bm  Predefined. */
3346/* EVSYS_CHMUX0_bp  Predefined. */
3347/* EVSYS_CHMUX1_bm  Predefined. */
3348/* EVSYS_CHMUX1_bp  Predefined. */
3349/* EVSYS_CHMUX2_bm  Predefined. */
3350/* EVSYS_CHMUX2_bp  Predefined. */
3351/* EVSYS_CHMUX3_bm  Predefined. */
3352/* EVSYS_CHMUX3_bp  Predefined. */
3353/* EVSYS_CHMUX4_bm  Predefined. */
3354/* EVSYS_CHMUX4_bp  Predefined. */
3355/* EVSYS_CHMUX5_bm  Predefined. */
3356/* EVSYS_CHMUX5_bp  Predefined. */
3357/* EVSYS_CHMUX6_bm  Predefined. */
3358/* EVSYS_CHMUX6_bp  Predefined. */
3359/* EVSYS_CHMUX7_bm  Predefined. */
3360/* EVSYS_CHMUX7_bp  Predefined. */
3361
3362
3363/* EVSYS.CH3MUX  bit masks and bit positions */
3364/* EVSYS_CHMUX_gm  Predefined. */
3365/* EVSYS_CHMUX_gp  Predefined. */
3366/* EVSYS_CHMUX0_bm  Predefined. */
3367/* EVSYS_CHMUX0_bp  Predefined. */
3368/* EVSYS_CHMUX1_bm  Predefined. */
3369/* EVSYS_CHMUX1_bp  Predefined. */
3370/* EVSYS_CHMUX2_bm  Predefined. */
3371/* EVSYS_CHMUX2_bp  Predefined. */
3372/* EVSYS_CHMUX3_bm  Predefined. */
3373/* EVSYS_CHMUX3_bp  Predefined. */
3374/* EVSYS_CHMUX4_bm  Predefined. */
3375/* EVSYS_CHMUX4_bp  Predefined. */
3376/* EVSYS_CHMUX5_bm  Predefined. */
3377/* EVSYS_CHMUX5_bp  Predefined. */
3378/* EVSYS_CHMUX6_bm  Predefined. */
3379/* EVSYS_CHMUX6_bp  Predefined. */
3380/* EVSYS_CHMUX7_bm  Predefined. */
3381/* EVSYS_CHMUX7_bp  Predefined. */
3382
3383
3384/* EVSYS.CH0CTRL  bit masks and bit positions */
3385#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
3386#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
3387#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
3388#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
3389#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
3390#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
3391
3392#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
3393#define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
3394
3395#define EVSYS_QDEN_bm  0x08  /* Quadrature Decoder Enable bit mask. */
3396#define EVSYS_QDEN_bp  3  /* Quadrature Decoder Enable bit position. */
3397
3398#define EVSYS_DIGFILT_gm  0x07  /* Digital Filter group mask. */
3399#define EVSYS_DIGFILT_gp  0  /* Digital Filter group position. */
3400#define EVSYS_DIGFILT0_bm  (1<<0)  /* Digital Filter bit 0 mask. */
3401#define EVSYS_DIGFILT0_bp  0  /* Digital Filter bit 0 position. */
3402#define EVSYS_DIGFILT1_bm  (1<<1)  /* Digital Filter bit 1 mask. */
3403#define EVSYS_DIGFILT1_bp  1  /* Digital Filter bit 1 position. */
3404#define EVSYS_DIGFILT2_bm  (1<<2)  /* Digital Filter bit 2 mask. */
3405#define EVSYS_DIGFILT2_bp  2  /* Digital Filter bit 2 position. */
3406
3407
3408/* EVSYS.CH1CTRL  bit masks and bit positions */
3409/* EVSYS_DIGFILT_gm  Predefined. */
3410/* EVSYS_DIGFILT_gp  Predefined. */
3411/* EVSYS_DIGFILT0_bm  Predefined. */
3412/* EVSYS_DIGFILT0_bp  Predefined. */
3413/* EVSYS_DIGFILT1_bm  Predefined. */
3414/* EVSYS_DIGFILT1_bp  Predefined. */
3415/* EVSYS_DIGFILT2_bm  Predefined. */
3416/* EVSYS_DIGFILT2_bp  Predefined. */
3417
3418
3419/* EVSYS.CH2CTRL  bit masks and bit positions */
3420/* EVSYS_QDIRM_gm  Predefined. */
3421/* EVSYS_QDIRM_gp  Predefined. */
3422/* EVSYS_QDIRM0_bm  Predefined. */
3423/* EVSYS_QDIRM0_bp  Predefined. */
3424/* EVSYS_QDIRM1_bm  Predefined. */
3425/* EVSYS_QDIRM1_bp  Predefined. */
3426
3427/* EVSYS_QDIEN_bm  Predefined. */
3428/* EVSYS_QDIEN_bp  Predefined. */
3429
3430/* EVSYS_QDEN_bm  Predefined. */
3431/* EVSYS_QDEN_bp  Predefined. */
3432
3433/* EVSYS_DIGFILT_gm  Predefined. */
3434/* EVSYS_DIGFILT_gp  Predefined. */
3435/* EVSYS_DIGFILT0_bm  Predefined. */
3436/* EVSYS_DIGFILT0_bp  Predefined. */
3437/* EVSYS_DIGFILT1_bm  Predefined. */
3438/* EVSYS_DIGFILT1_bp  Predefined. */
3439/* EVSYS_DIGFILT2_bm  Predefined. */
3440/* EVSYS_DIGFILT2_bp  Predefined. */
3441
3442
3443/* EVSYS.CH3CTRL  bit masks and bit positions */
3444/* EVSYS_DIGFILT_gm  Predefined. */
3445/* EVSYS_DIGFILT_gp  Predefined. */
3446/* EVSYS_DIGFILT0_bm  Predefined. */
3447/* EVSYS_DIGFILT0_bp  Predefined. */
3448/* EVSYS_DIGFILT1_bm  Predefined. */
3449/* EVSYS_DIGFILT1_bp  Predefined. */
3450/* EVSYS_DIGFILT2_bm  Predefined. */
3451/* EVSYS_DIGFILT2_bp  Predefined. */
3452
3453
3454/* NVM - Non Volatile Memory Controller */
3455/* NVM.CMD  bit masks and bit positions */
3456#define NVM_CMD_gm  0xFF  /* Command group mask. */
3457#define NVM_CMD_gp  0  /* Command group position. */
3458#define NVM_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
3459#define NVM_CMD0_bp  0  /* Command bit 0 position. */
3460#define NVM_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
3461#define NVM_CMD1_bp  1  /* Command bit 1 position. */
3462#define NVM_CMD2_bm  (1<<2)  /* Command bit 2 mask. */
3463#define NVM_CMD2_bp  2  /* Command bit 2 position. */
3464#define NVM_CMD3_bm  (1<<3)  /* Command bit 3 mask. */
3465#define NVM_CMD3_bp  3  /* Command bit 3 position. */
3466#define NVM_CMD4_bm  (1<<4)  /* Command bit 4 mask. */
3467#define NVM_CMD4_bp  4  /* Command bit 4 position. */
3468#define NVM_CMD5_bm  (1<<5)  /* Command bit 5 mask. */
3469#define NVM_CMD5_bp  5  /* Command bit 5 position. */
3470#define NVM_CMD6_bm  (1<<6)  /* Command bit 6 mask. */
3471#define NVM_CMD6_bp  6  /* Command bit 6 position. */
3472#define NVM_CMD7_bm  (1<<7)  /* Command bit 7 mask. */
3473#define NVM_CMD7_bp  7  /* Command bit 7 position. */
3474
3475
3476/* NVM.CTRLA  bit masks and bit positions */
3477#define NVM_CMDEX_bm  0x01  /* Command Execute bit mask. */
3478#define NVM_CMDEX_bp  0  /* Command Execute bit position. */
3479
3480
3481/* NVM.CTRLB  bit masks and bit positions */
3482#define NVM_EEMAPEN_bm  0x08  /* EEPROM Mapping Enable bit mask. */
3483#define NVM_EEMAPEN_bp  3  /* EEPROM Mapping Enable bit position. */
3484
3485#define NVM_FPRM_bm  0x04  /* Flash Power Reduction Enable bit mask. */
3486#define NVM_FPRM_bp  2  /* Flash Power Reduction Enable bit position. */
3487
3488#define NVM_EPRM_bm  0x02  /* EEPROM Power Reduction Enable bit mask. */
3489#define NVM_EPRM_bp  1  /* EEPROM Power Reduction Enable bit position. */
3490
3491#define NVM_SPMLOCK_bm  0x01  /* SPM Lock bit mask. */
3492#define NVM_SPMLOCK_bp  0  /* SPM Lock bit position. */
3493
3494
3495/* NVM.INTCTRL  bit masks and bit positions */
3496#define NVM_SPMLVL_gm  0x0C  /* SPM Interrupt Level group mask. */
3497#define NVM_SPMLVL_gp  2  /* SPM Interrupt Level group position. */
3498#define NVM_SPMLVL0_bm  (1<<2)  /* SPM Interrupt Level bit 0 mask. */
3499#define NVM_SPMLVL0_bp  2  /* SPM Interrupt Level bit 0 position. */
3500#define NVM_SPMLVL1_bm  (1<<3)  /* SPM Interrupt Level bit 1 mask. */
3501#define NVM_SPMLVL1_bp  3  /* SPM Interrupt Level bit 1 position. */
3502
3503#define NVM_EELVL_gm  0x03  /* EEPROM Interrupt Level group mask. */
3504#define NVM_EELVL_gp  0  /* EEPROM Interrupt Level group position. */
3505#define NVM_EELVL0_bm  (1<<0)  /* EEPROM Interrupt Level bit 0 mask. */
3506#define NVM_EELVL0_bp  0  /* EEPROM Interrupt Level bit 0 position. */
3507#define NVM_EELVL1_bm  (1<<1)  /* EEPROM Interrupt Level bit 1 mask. */
3508#define NVM_EELVL1_bp  1  /* EEPROM Interrupt Level bit 1 position. */
3509
3510
3511/* NVM.STATUS  bit masks and bit positions */
3512#define NVM_NVMBUSY_bm  0x80  /* Non-volatile Memory Busy bit mask. */
3513#define NVM_NVMBUSY_bp  7  /* Non-volatile Memory Busy bit position. */
3514
3515#define NVM_FBUSY_bm  0x40  /* Flash Memory Busy bit mask. */
3516#define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
3517
3518#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
3519#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
3520
3521#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
3522#define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
3523
3524
3525/* NVM.LOCKBITS  bit masks and bit positions */
3526#define NVM_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3527#define NVM_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3528#define NVM_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3529#define NVM_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3530#define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3531#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3532
3533#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3534#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3535#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3536#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3537#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3538#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3539
3540#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3541#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3542#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3543#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3544#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3545#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3546
3547#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
3548#define NVM_LB_gp  0  /* Lock Bits group position. */
3549#define NVM_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3550#define NVM_LB0_bp  0  /* Lock Bits bit 0 position. */
3551#define NVM_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3552#define NVM_LB1_bp  1  /* Lock Bits bit 1 position. */
3553
3554
3555/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
3556#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
3557#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
3558#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
3559#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
3560#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
3561#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
3562
3563#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
3564#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
3565#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
3566#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
3567#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
3568#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
3569
3570#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
3571#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
3572#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
3573#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
3574#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
3575#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
3576
3577#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
3578#define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
3579#define NVM_LOCKBITS_LB0_bm  (1<<0)  /* Lock Bits bit 0 mask. */
3580#define NVM_LOCKBITS_LB0_bp  0  /* Lock Bits bit 0 position. */
3581#define NVM_LOCKBITS_LB1_bm  (1<<1)  /* Lock Bits bit 1 mask. */
3582#define NVM_LOCKBITS_LB1_bp  1  /* Lock Bits bit 1 position. */
3583
3584
3585/* NVM_FUSES.FUSEBYTE0  bit masks and bit positions */
3586#define NVM_FUSES_USERID_gm  0xFF  /* User ID group mask. */
3587#define NVM_FUSES_USERID_gp  0  /* User ID group position. */
3588#define NVM_FUSES_USERID0_bm  (1<<0)  /* User ID bit 0 mask. */
3589#define NVM_FUSES_USERID0_bp  0  /* User ID bit 0 position. */
3590#define NVM_FUSES_USERID1_bm  (1<<1)  /* User ID bit 1 mask. */
3591#define NVM_FUSES_USERID1_bp  1  /* User ID bit 1 position. */
3592#define NVM_FUSES_USERID2_bm  (1<<2)  /* User ID bit 2 mask. */
3593#define NVM_FUSES_USERID2_bp  2  /* User ID bit 2 position. */
3594#define NVM_FUSES_USERID3_bm  (1<<3)  /* User ID bit 3 mask. */
3595#define NVM_FUSES_USERID3_bp  3  /* User ID bit 3 position. */
3596#define NVM_FUSES_USERID4_bm  (1<<4)  /* User ID bit 4 mask. */
3597#define NVM_FUSES_USERID4_bp  4  /* User ID bit 4 position. */
3598#define NVM_FUSES_USERID5_bm  (1<<5)  /* User ID bit 5 mask. */
3599#define NVM_FUSES_USERID5_bp  5  /* User ID bit 5 position. */
3600#define NVM_FUSES_USERID6_bm  (1<<6)  /* User ID bit 6 mask. */
3601#define NVM_FUSES_USERID6_bp  6  /* User ID bit 6 position. */
3602#define NVM_FUSES_USERID7_bm  (1<<7)  /* User ID bit 7 mask. */
3603#define NVM_FUSES_USERID7_bp  7  /* User ID bit 7 position. */
3604
3605
3606/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
3607#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
3608#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
3609#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
3610#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
3611#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
3612#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
3613#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
3614#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
3615#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
3616#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
3617
3618#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
3619#define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
3620#define NVM_FUSES_WDP0_bm  (1<<0)  /* Watchdog Timeout Period bit 0 mask. */
3621#define NVM_FUSES_WDP0_bp  0  /* Watchdog Timeout Period bit 0 position. */
3622#define NVM_FUSES_WDP1_bm  (1<<1)  /* Watchdog Timeout Period bit 1 mask. */
3623#define NVM_FUSES_WDP1_bp  1  /* Watchdog Timeout Period bit 1 position. */
3624#define NVM_FUSES_WDP2_bm  (1<<2)  /* Watchdog Timeout Period bit 2 mask. */
3625#define NVM_FUSES_WDP2_bp  2  /* Watchdog Timeout Period bit 2 position. */
3626#define NVM_FUSES_WDP3_bm  (1<<3)  /* Watchdog Timeout Period bit 3 mask. */
3627#define NVM_FUSES_WDP3_bp  3  /* Watchdog Timeout Period bit 3 position. */
3628
3629
3630/* NVM_FUSES.FUSEBYTE2  bit masks and bit positions */
3631#define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
3632#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
3633
3634#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
3635#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
3636
3637#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
3638#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
3639#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
3640#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
3641#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
3642#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
3643
3644
3645/* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
3646#define NVM_FUSES_SUT_gm  0x0C  /* Start-up Time group mask. */
3647#define NVM_FUSES_SUT_gp  2  /* Start-up Time group position. */
3648#define NVM_FUSES_SUT0_bm  (1<<2)  /* Start-up Time bit 0 mask. */
3649#define NVM_FUSES_SUT0_bp  2  /* Start-up Time bit 0 position. */
3650#define NVM_FUSES_SUT1_bm  (1<<3)  /* Start-up Time bit 1 mask. */
3651#define NVM_FUSES_SUT1_bp  3  /* Start-up Time bit 1 position. */
3652
3653#define NVM_FUSES_WDLOCK_bm  0x02  /* Watchdog Timer Lock bit mask. */
3654#define NVM_FUSES_WDLOCK_bp  1  /* Watchdog Timer Lock bit position. */
3655
3656
3657/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
3658#define NVM_FUSES_BODACT_gm  0x30  /* BOD Operation in Active Mode group mask. */
3659#define NVM_FUSES_BODACT_gp  4  /* BOD Operation in Active Mode group position. */
3660#define NVM_FUSES_BODACT0_bm  (1<<4)  /* BOD Operation in Active Mode bit 0 mask. */
3661#define NVM_FUSES_BODACT0_bp  4  /* BOD Operation in Active Mode bit 0 position. */
3662#define NVM_FUSES_BODACT1_bm  (1<<5)  /* BOD Operation in Active Mode bit 1 mask. */
3663#define NVM_FUSES_BODACT1_bp  5  /* BOD Operation in Active Mode bit 1 position. */
3664
3665#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
3666#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
3667
3668#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
3669#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
3670#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
3671#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
3672#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
3673#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
3674#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
3675#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
3676
3677
3678/* AC - Analog Comparator */
3679/* AC.AC0CTRL  bit masks and bit positions */
3680#define AC_INTMODE_gm  0xC0  /* Interrupt Mode group mask. */
3681#define AC_INTMODE_gp  6  /* Interrupt Mode group position. */
3682#define AC_INTMODE0_bm  (1<<6)  /* Interrupt Mode bit 0 mask. */
3683#define AC_INTMODE0_bp  6  /* Interrupt Mode bit 0 position. */
3684#define AC_INTMODE1_bm  (1<<7)  /* Interrupt Mode bit 1 mask. */
3685#define AC_INTMODE1_bp  7  /* Interrupt Mode bit 1 position. */
3686
3687#define AC_INTLVL_gm  0x30  /* Interrupt Level group mask. */
3688#define AC_INTLVL_gp  4  /* Interrupt Level group position. */
3689#define AC_INTLVL0_bm  (1<<4)  /* Interrupt Level bit 0 mask. */
3690#define AC_INTLVL0_bp  4  /* Interrupt Level bit 0 position. */
3691#define AC_INTLVL1_bm  (1<<5)  /* Interrupt Level bit 1 mask. */
3692#define AC_INTLVL1_bp  5  /* Interrupt Level bit 1 position. */
3693
3694#define AC_HSMODE_bm  0x08  /* High-speed Mode bit mask. */
3695#define AC_HSMODE_bp  3  /* High-speed Mode bit position. */
3696
3697#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
3698#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
3699#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
3700#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
3701#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
3702#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */
3703
3704#define AC_ENABLE_bm  0x01  /* Enable bit mask. */
3705#define AC_ENABLE_bp  0  /* Enable bit position. */
3706
3707
3708/* AC.AC1CTRL  bit masks and bit positions */
3709/* AC_INTMODE_gm  Predefined. */
3710/* AC_INTMODE_gp  Predefined. */
3711/* AC_INTMODE0_bm  Predefined. */
3712/* AC_INTMODE0_bp  Predefined. */
3713/* AC_INTMODE1_bm  Predefined. */
3714/* AC_INTMODE1_bp  Predefined. */
3715
3716/* AC_INTLVL_gm  Predefined. */
3717/* AC_INTLVL_gp  Predefined. */
3718/* AC_INTLVL0_bm  Predefined. */
3719/* AC_INTLVL0_bp  Predefined. */
3720/* AC_INTLVL1_bm  Predefined. */
3721/* AC_INTLVL1_bp  Predefined. */
3722
3723/* AC_HSMODE_bm  Predefined. */
3724/* AC_HSMODE_bp  Predefined. */
3725
3726/* AC_HYSMODE_gm  Predefined. */
3727/* AC_HYSMODE_gp  Predefined. */
3728/* AC_HYSMODE0_bm  Predefined. */
3729/* AC_HYSMODE0_bp  Predefined. */
3730/* AC_HYSMODE1_bm  Predefined. */
3731/* AC_HYSMODE1_bp  Predefined. */
3732
3733/* AC_ENABLE_bm  Predefined. */
3734/* AC_ENABLE_bp  Predefined. */
3735
3736
3737/* AC.AC0MUXCTRL  bit masks and bit positions */
3738#define AC_MUXPOS_gm  0x38  /* MUX Positive Input group mask. */
3739#define AC_MUXPOS_gp  3  /* MUX Positive Input group position. */
3740#define AC_MUXPOS0_bm  (1<<3)  /* MUX Positive Input bit 0 mask. */
3741#define AC_MUXPOS0_bp  3  /* MUX Positive Input bit 0 position. */
3742#define AC_MUXPOS1_bm  (1<<4)  /* MUX Positive Input bit 1 mask. */
3743#define AC_MUXPOS1_bp  4  /* MUX Positive Input bit 1 position. */
3744#define AC_MUXPOS2_bm  (1<<5)  /* MUX Positive Input bit 2 mask. */
3745#define AC_MUXPOS2_bp  5  /* MUX Positive Input bit 2 position. */
3746
3747#define AC_MUXNEG_gm  0x07  /* MUX Negative Input group mask. */
3748#define AC_MUXNEG_gp  0  /* MUX Negative Input group position. */
3749#define AC_MUXNEG0_bm  (1<<0)  /* MUX Negative Input bit 0 mask. */
3750#define AC_MUXNEG0_bp  0  /* MUX Negative Input bit 0 position. */
3751#define AC_MUXNEG1_bm  (1<<1)  /* MUX Negative Input bit 1 mask. */
3752#define AC_MUXNEG1_bp  1  /* MUX Negative Input bit 1 position. */
3753#define AC_MUXNEG2_bm  (1<<2)  /* MUX Negative Input bit 2 mask. */
3754#define AC_MUXNEG2_bp  2  /* MUX Negative Input bit 2 position. */
3755
3756
3757/* AC.AC1MUXCTRL  bit masks and bit positions */
3758/* AC_MUXPOS_gm  Predefined. */
3759/* AC_MUXPOS_gp  Predefined. */
3760/* AC_MUXPOS0_bm  Predefined. */
3761/* AC_MUXPOS0_bp  Predefined. */
3762/* AC_MUXPOS1_bm  Predefined. */
3763/* AC_MUXPOS1_bp  Predefined. */
3764/* AC_MUXPOS2_bm  Predefined. */
3765/* AC_MUXPOS2_bp  Predefined. */
3766
3767/* AC_MUXNEG_gm  Predefined. */
3768/* AC_MUXNEG_gp  Predefined. */
3769/* AC_MUXNEG0_bm  Predefined. */
3770/* AC_MUXNEG0_bp  Predefined. */
3771/* AC_MUXNEG1_bm  Predefined. */
3772/* AC_MUXNEG1_bp  Predefined. */
3773/* AC_MUXNEG2_bm  Predefined. */
3774/* AC_MUXNEG2_bp  Predefined. */
3775
3776
3777/* AC.CTRLA  bit masks and bit positions */
3778#define AC_AC0OUT_bm  0x01  /* Comparator 0 Output Enable bit mask. */
3779#define AC_AC0OUT_bp  0  /* Comparator 0 Output Enable bit position. */
3780
3781
3782/* AC.CTRLB  bit masks and bit positions */
3783#define AC_SCALEFAC_gm  0x3F  /* VCC Voltage Scaler Factor group mask. */
3784#define AC_SCALEFAC_gp  0  /* VCC Voltage Scaler Factor group position. */
3785#define AC_SCALEFAC0_bm  (1<<0)  /* VCC Voltage Scaler Factor bit 0 mask. */
3786#define AC_SCALEFAC0_bp  0  /* VCC Voltage Scaler Factor bit 0 position. */
3787#define AC_SCALEFAC1_bm  (1<<1)  /* VCC Voltage Scaler Factor bit 1 mask. */
3788#define AC_SCALEFAC1_bp  1  /* VCC Voltage Scaler Factor bit 1 position. */
3789#define AC_SCALEFAC2_bm  (1<<2)  /* VCC Voltage Scaler Factor bit 2 mask. */
3790#define AC_SCALEFAC2_bp  2  /* VCC Voltage Scaler Factor bit 2 position. */
3791#define AC_SCALEFAC3_bm  (1<<3)  /* VCC Voltage Scaler Factor bit 3 mask. */
3792#define AC_SCALEFAC3_bp  3  /* VCC Voltage Scaler Factor bit 3 position. */
3793#define AC_SCALEFAC4_bm  (1<<4)  /* VCC Voltage Scaler Factor bit 4 mask. */
3794#define AC_SCALEFAC4_bp  4  /* VCC Voltage Scaler Factor bit 4 position. */
3795#define AC_SCALEFAC5_bm  (1<<5)  /* VCC Voltage Scaler Factor bit 5 mask. */
3796#define AC_SCALEFAC5_bp  5  /* VCC Voltage Scaler Factor bit 5 position. */
3797
3798
3799/* AC.WINCTRL  bit masks and bit positions */
3800#define AC_WEN_bm  0x10  /* Window Mode Enable bit mask. */
3801#define AC_WEN_bp  4  /* Window Mode Enable bit position. */
3802
3803#define AC_WINTMODE_gm  0x0C  /* Window Interrupt Mode group mask. */
3804#define AC_WINTMODE_gp  2  /* Window Interrupt Mode group position. */
3805#define AC_WINTMODE0_bm  (1<<2)  /* Window Interrupt Mode bit 0 mask. */
3806#define AC_WINTMODE0_bp  2  /* Window Interrupt Mode bit 0 position. */
3807#define AC_WINTMODE1_bm  (1<<3)  /* Window Interrupt Mode bit 1 mask. */
3808#define AC_WINTMODE1_bp  3  /* Window Interrupt Mode bit 1 position. */
3809
3810#define AC_WINTLVL_gm  0x03  /* Window Interrupt Level group mask. */
3811#define AC_WINTLVL_gp  0  /* Window Interrupt Level group position. */
3812#define AC_WINTLVL0_bm  (1<<0)  /* Window Interrupt Level bit 0 mask. */
3813#define AC_WINTLVL0_bp  0  /* Window Interrupt Level bit 0 position. */
3814#define AC_WINTLVL1_bm  (1<<1)  /* Window Interrupt Level bit 1 mask. */
3815#define AC_WINTLVL1_bp  1  /* Window Interrupt Level bit 1 position. */
3816
3817
3818/* AC.STATUS  bit masks and bit positions */
3819#define AC_WSTATE_gm  0xC0  /* Window Mode State group mask. */
3820#define AC_WSTATE_gp  6  /* Window Mode State group position. */
3821#define AC_WSTATE0_bm  (1<<6)  /* Window Mode State bit 0 mask. */
3822#define AC_WSTATE0_bp  6  /* Window Mode State bit 0 position. */
3823#define AC_WSTATE1_bm  (1<<7)  /* Window Mode State bit 1 mask. */
3824#define AC_WSTATE1_bp  7  /* Window Mode State bit 1 position. */
3825
3826#define AC_AC1STATE_bm  0x20  /* Comparator 1 State bit mask. */
3827#define AC_AC1STATE_bp  5  /* Comparator 1 State bit position. */
3828
3829#define AC_AC0STATE_bm  0x10  /* Comparator 0 State bit mask. */
3830#define AC_AC0STATE_bp  4  /* Comparator 0 State bit position. */
3831
3832#define AC_WIF_bm  0x04  /* Window Mode Interrupt Flag bit mask. */
3833#define AC_WIF_bp  2  /* Window Mode Interrupt Flag bit position. */
3834
3835#define AC_AC1IF_bm  0x02  /* Comparator 1 Interrupt Flag bit mask. */
3836#define AC_AC1IF_bp  1  /* Comparator 1 Interrupt Flag bit position. */
3837
3838#define AC_AC0IF_bm  0x01  /* Comparator 0 Interrupt Flag bit mask. */
3839#define AC_AC0IF_bp  0  /* Comparator 0 Interrupt Flag bit position. */
3840
3841
3842/* ADC - Analog/Digital Converter */
3843/* ADC_CH.CTRL  bit masks and bit positions */
3844#define ADC_CH_START_bm  0x80  /* Channel Start Conversion bit mask. */
3845#define ADC_CH_START_bp  7  /* Channel Start Conversion bit position. */
3846
3847#define ADC_CH_GAINFAC_gm  0x1C  /* Gain Factor group mask. */
3848#define ADC_CH_GAINFAC_gp  2  /* Gain Factor group position. */
3849#define ADC_CH_GAINFAC0_bm  (1<<2)  /* Gain Factor bit 0 mask. */
3850#define ADC_CH_GAINFAC0_bp  2  /* Gain Factor bit 0 position. */
3851#define ADC_CH_GAINFAC1_bm  (1<<3)  /* Gain Factor bit 1 mask. */
3852#define ADC_CH_GAINFAC1_bp  3  /* Gain Factor bit 1 position. */
3853#define ADC_CH_GAINFAC2_bm  (1<<4)  /* Gain Factor bit 2 mask. */
3854#define ADC_CH_GAINFAC2_bp  4  /* Gain Factor bit 2 position. */
3855
3856#define ADC_CH_INPUTMODE_gm  0x03  /* Input Mode Select group mask. */
3857#define ADC_CH_INPUTMODE_gp  0  /* Input Mode Select group position. */
3858#define ADC_CH_INPUTMODE0_bm  (1<<0)  /* Input Mode Select bit 0 mask. */
3859#define ADC_CH_INPUTMODE0_bp  0  /* Input Mode Select bit 0 position. */
3860#define ADC_CH_INPUTMODE1_bm  (1<<1)  /* Input Mode Select bit 1 mask. */
3861#define ADC_CH_INPUTMODE1_bp  1  /* Input Mode Select bit 1 position. */
3862
3863
3864/* ADC_CH.MUXCTRL  bit masks and bit positions */
3865#define ADC_CH_MUXPOS_gm  0x78  /* Positive Input Select group mask. */
3866#define ADC_CH_MUXPOS_gp  3  /* Positive Input Select group position. */
3867#define ADC_CH_MUXPOS0_bm  (1<<3)  /* Positive Input Select bit 0 mask. */
3868#define ADC_CH_MUXPOS0_bp  3  /* Positive Input Select bit 0 position. */
3869#define ADC_CH_MUXPOS1_bm  (1<<4)  /* Positive Input Select bit 1 mask. */
3870#define ADC_CH_MUXPOS1_bp  4  /* Positive Input Select bit 1 position. */
3871#define ADC_CH_MUXPOS2_bm  (1<<5)  /* Positive Input Select bit 2 mask. */
3872#define ADC_CH_MUXPOS2_bp  5  /* Positive Input Select bit 2 position. */
3873#define ADC_CH_MUXPOS3_bm  (1<<6)  /* Positive Input Select bit 3 mask. */
3874#define ADC_CH_MUXPOS3_bp  6  /* Positive Input Select bit 3 position. */
3875#define ADC_CH_MUXPOS4_bm  (1<<7)  /* Positive Input Select bit 3 mask. */
3876#define ADC_CH_MUXPOS4_bp  7  /* Positive Input Select bit 3 position. */
3877
3878#define ADC_CH_MUXINT_gm  0x78  /* Internal Input Select group mask. */
3879#define ADC_CH_MUXINT_gp  3  /* Internal Input Select group position. */
3880#define ADC_CH_MUXINT0_bm  (1<<3)  /* Internal Input Select bit 0 mask. */
3881#define ADC_CH_MUXINT0_bp  3  /* Internal Input Select bit 0 position. */
3882#define ADC_CH_MUXINT1_bm  (1<<4)  /* Internal Input Select bit 1 mask. */
3883#define ADC_CH_MUXINT1_bp  4  /* Internal Input Select bit 1 position. */
3884#define ADC_CH_MUXINT2_bm  (1<<5)  /* Internal Input Select bit 2 mask. */
3885#define ADC_CH_MUXINT2_bp  5  /* Internal Input Select bit 2 position. */
3886#define ADC_CH_MUXINT3_bm  (1<<6)  /* Internal Input Select bit 3 mask. */
3887#define ADC_CH_MUXINT3_bp  6  /* Internal Input Select bit 3 position. */
3888
3889#define ADC_CH_MUXNEG_gm  0x03  /* Negative Input Select group mask. */
3890#define ADC_CH_MUXNEG_gp  0  /* Negative Input Select group position. */
3891#define ADC_CH_MUXNEG0_bm  (1<<0)  /* Negative Input Select bit 0 mask. */
3892#define ADC_CH_MUXNEG0_bp  0  /* Negative Input Select bit 0 position. */
3893#define ADC_CH_MUXNEG1_bm  (1<<1)  /* Negative Input Select bit 1 mask. */
3894#define ADC_CH_MUXNEG1_bp  1  /* Negative Input Select bit 1 position. */
3895
3896
3897/* ADC_CH.INTCTRL  bit masks and bit positions */
3898#define ADC_CH_INTMODE_gm  0x0C  /* Interrupt Mode group mask. */
3899#define ADC_CH_INTMODE_gp  2  /* Interrupt Mode group position. */
3900#define ADC_CH_INTMODE0_bm  (1<<2)  /* Interrupt Mode bit 0 mask. */
3901#define ADC_CH_INTMODE0_bp  2  /* Interrupt Mode bit 0 position. */
3902#define ADC_CH_INTMODE1_bm  (1<<3)  /* Interrupt Mode bit 1 mask. */
3903#define ADC_CH_INTMODE1_bp  3  /* Interrupt Mode bit 1 position. */
3904
3905#define ADC_CH_INTLVL_gm  0x03  /* Interrupt Level group mask. */
3906#define ADC_CH_INTLVL_gp  0  /* Interrupt Level group position. */
3907#define ADC_CH_INTLVL0_bm  (1<<0)  /* Interrupt Level bit 0 mask. */
3908#define ADC_CH_INTLVL0_bp  0  /* Interrupt Level bit 0 position. */
3909#define ADC_CH_INTLVL1_bm  (1<<1)  /* Interrupt Level bit 1 mask. */
3910#define ADC_CH_INTLVL1_bp  1  /* Interrupt Level bit 1 position. */
3911
3912
3913/* ADC_CH.INTFLAGS  bit masks and bit positions */
3914#define ADC_CH_CHIF_bm  0x01  /* Channel Interrupt Flag bit mask. */
3915#define ADC_CH_CHIF_bp  0  /* Channel Interrupt Flag bit position. */
3916
3917
3918/* ADC.CTRLA  bit masks and bit positions */
3919#define ADC_CH0START_bm  0x04  /* Channel 0 Start Conversion bit mask. */
3920#define ADC_CH0START_bp  2  /* Channel 0 Start Conversion bit position. */
3921
3922#define ADC_FLUSH_bm  0x02  /* ADC Flush bit mask. */
3923#define ADC_FLUSH_bp  1  /* ADC Flush bit position. */
3924
3925#define ADC_ENABLE_bm  0x01  /* Enable ADC bit mask. */
3926#define ADC_ENABLE_bp  0  /* Enable ADC bit position. */
3927
3928
3929/* ADC.CTRLB  bit masks and bit positions */
3930#define ADC_IMPMODE_bm  0x80  /* Impedance Mode bit mask. */
3931#define ADC_IMPMODE_bp  7  /* Impedance Mode bit position. */
3932
3933#define ADC_CURRENT_bm  0x60  /* Current bit mask. */
3934#define ADC_CURRENT1_bp  6  /* Current bit position. */
3935#define ADC_CURRENT0_bp  5  /* Current bit position. */
3936
3937#define ADC_CONMODE_bm  0x10  /* Conversion Mode bit mask. */
3938#define ADC_CONMODE_bp  4  /* Conversion Mode bit position. */
3939
3940#define ADC_FREERUN_bm  0x08  /* Free Running Mode Enable bit mask. */
3941#define ADC_FREERUN_bp  3  /* Free Running Mode Enable bit position. */
3942
3943#define ADC_RESOLUTION_gm  0x06  /* Result Resolution group mask. */
3944#define ADC_RESOLUTION_gp  1  /* Result Resolution group position. */
3945#define ADC_RESOLUTION0_bm  (1<<1)  /* Result Resolution bit 0 mask. */
3946#define ADC_RESOLUTION0_bp  1  /* Result Resolution bit 0 position. */
3947#define ADC_RESOLUTION1_bm  (1<<2)  /* Result Resolution bit 1 mask. */
3948#define ADC_RESOLUTION1_bp  2  /* Result Resolution bit 1 position. */
3949
3950
3951/* ADC.REFCTRL  bit masks and bit positions */
3952#define ADC_REFSEL_gm  0x70  /* Reference Selection group mask. */
3953#define ADC_REFSEL_gp  4  /* Reference Selection group position. */
3954#define ADC_REFSEL0_bm  (1<<4)  /* Reference Selection bit 0 mask. */
3955#define ADC_REFSEL0_bp  4  /* Reference Selection bit 0 position. */
3956#define ADC_REFSEL1_bm  (1<<5)  /* Reference Selection bit 1 mask. */
3957#define ADC_REFSEL1_bp  5  /* Reference Selection bit 1 position. */
3958#define ADC_REFSEL2_bm  (1<<6)  /* Reference Selection bit 2 mask. */
3959#define ADC_REFSEL2_bp  6  /* Reference Selection bit 2 position. */
3960
3961#define ADC_BANDGAP_bm  0x02  /* Bandgap enable bit mask. */
3962#define ADC_BANDGAP_bp  1  /* Bandgap enable bit position. */
3963
3964#define ADC_TEMPREF_bm  0x01  /* Temperature Reference Enable bit mask. */
3965#define ADC_TEMPREF_bp  0  /* Temperature Reference Enable bit position. */
3966
3967
3968/* ADC.EVCTRL  bit masks and bit positions */
3969#define ADC_SWEEP_gm  0xC0  /* Channel Sweep Selection group mask. */
3970#define ADC_SWEEP_gp  6  /* Channel Sweep Selection group position. */
3971#define ADC_SWEEP0_bm  (1<<6)  /* Channel Sweep Selection bit 0 mask. */
3972#define ADC_SWEEP0_bp  6  /* Channel Sweep Selection bit 0 position. */
3973#define ADC_SWEEP1_bm  (1<<7)  /* Channel Sweep Selection bit 1 mask. */
3974#define ADC_SWEEP1_bp  7  /* Channel Sweep Selection bit 1 position. */
3975
3976#define ADC_EVSEL_gm  0x38  /* Event Input Select group mask. */
3977#define ADC_EVSEL_gp  3  /* Event Input Select group position. */
3978#define ADC_EVSEL0_bm  (1<<3)  /* Event Input Select bit 0 mask. */
3979#define ADC_EVSEL0_bp  3  /* Event Input Select bit 0 position. */
3980#define ADC_EVSEL1_bm  (1<<4)  /* Event Input Select bit 1 mask. */
3981#define ADC_EVSEL1_bp  4  /* Event Input Select bit 1 position. */
3982#define ADC_EVSEL2_bm  (1<<5)  /* Event Input Select bit 2 mask. */
3983#define ADC_EVSEL2_bp  5  /* Event Input Select bit 2 position. */
3984
3985#define ADC_EVACT_gm  0x07  /* Event Action Select group mask. */
3986#define ADC_EVACT_gp  0  /* Event Action Select group position. */
3987#define ADC_EVACT0_bm  (1<<0)  /* Event Action Select bit 0 mask. */
3988#define ADC_EVACT0_bp  0  /* Event Action Select bit 0 position. */
3989#define ADC_EVACT1_bm  (1<<1)  /* Event Action Select bit 1 mask. */
3990#define ADC_EVACT1_bp  1  /* Event Action Select bit 1 position. */
3991#define ADC_EVACT2_bm  (1<<2)  /* Event Action Select bit 2 mask. */
3992#define ADC_EVACT2_bp  2  /* Event Action Select bit 2 position. */
3993
3994
3995/* ADC.PRESCALER  bit masks and bit positions */
3996#define ADC_PRESCALER_gm  0x07  /* Clock Prescaler Selection group mask. */
3997#define ADC_PRESCALER_gp  0  /* Clock Prescaler Selection group position. */
3998#define ADC_PRESCALER0_bm  (1<<0)  /* Clock Prescaler Selection bit 0 mask. */
3999#define ADC_PRESCALER0_bp  0  /* Clock Prescaler Selection bit 0 position. */
4000#define ADC_PRESCALER1_bm  (1<<1)  /* Clock Prescaler Selection bit 1 mask. */
4001#define ADC_PRESCALER1_bp  1  /* Clock Prescaler Selection bit 1 position. */
4002#define ADC_PRESCALER2_bm  (1<<2)  /* Clock Prescaler Selection bit 2 mask. */
4003#define ADC_PRESCALER2_bp  2  /* Clock Prescaler Selection bit 2 position. */
4004
4005
4006/* ADC.INTFLAGS  bit masks and bit positions */
4007#define ADC_CH0IF_bm  0x01  /* Channel 0 Interrupt Flag bit mask. */
4008#define ADC_CH0IF_bp  0  /* Channel 0 Interrupt Flag bit position. */
4009
4010
4011/* RTC - Real-Time Clounter */
4012/* RTC.CTRL  bit masks and bit positions */
4013#define RTC_PRESCALER_gm  0x07  /* Prescaling Factor group mask. */
4014#define RTC_PRESCALER_gp  0  /* Prescaling Factor group position. */
4015#define RTC_PRESCALER0_bm  (1<<0)  /* Prescaling Factor bit 0 mask. */
4016#define RTC_PRESCALER0_bp  0  /* Prescaling Factor bit 0 position. */
4017#define RTC_PRESCALER1_bm  (1<<1)  /* Prescaling Factor bit 1 mask. */
4018#define RTC_PRESCALER1_bp  1  /* Prescaling Factor bit 1 position. */
4019#define RTC_PRESCALER2_bm  (1<<2)  /* Prescaling Factor bit 2 mask. */
4020#define RTC_PRESCALER2_bp  2  /* Prescaling Factor bit 2 position. */
4021
4022
4023/* RTC.STATUS  bit masks and bit positions */
4024#define RTC_SYNCBUSY_bm  0x01  /* Synchronization Busy Flag bit mask. */
4025#define RTC_SYNCBUSY_bp  0  /* Synchronization Busy Flag bit position. */
4026
4027
4028/* RTC.INTCTRL  bit masks and bit positions */
4029#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
4030#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
4031#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
4032#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
4033#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
4034#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
4035
4036#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
4037#define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
4038#define RTC_OVFINTLVL0_bm  (1<<0)  /* Overflow Interrupt Level bit 0 mask. */
4039#define RTC_OVFINTLVL0_bp  0  /* Overflow Interrupt Level bit 0 position. */
4040#define RTC_OVFINTLVL1_bm  (1<<1)  /* Overflow Interrupt Level bit 1 mask. */
4041#define RTC_OVFINTLVL1_bp  1  /* Overflow Interrupt Level bit 1 position. */
4042
4043
4044/* RTC.INTFLAGS  bit masks and bit positions */
4045#define RTC_COMPIF_bm  0x02  /* Compare Match Interrupt Flag bit mask. */
4046#define RTC_COMPIF_bp  1  /* Compare Match Interrupt Flag bit position. */
4047
4048#define RTC_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4049#define RTC_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4050
4051
4052/* EBI - External Bus Interface */
4053/* EBI_CS.CTRLA  bit masks and bit positions */
4054#define EBI_CS_ASIZE_gm  0x7C  /* Address Size group mask. */
4055#define EBI_CS_ASIZE_gp  2  /* Address Size group position. */
4056#define EBI_CS_ASIZE0_bm  (1<<2)  /* Address Size bit 0 mask. */
4057#define EBI_CS_ASIZE0_bp  2  /* Address Size bit 0 position. */
4058#define EBI_CS_ASIZE1_bm  (1<<3)  /* Address Size bit 1 mask. */
4059#define EBI_CS_ASIZE1_bp  3  /* Address Size bit 1 position. */
4060#define EBI_CS_ASIZE2_bm  (1<<4)  /* Address Size bit 2 mask. */
4061#define EBI_CS_ASIZE2_bp  4  /* Address Size bit 2 position. */
4062#define EBI_CS_ASIZE3_bm  (1<<5)  /* Address Size bit 3 mask. */
4063#define EBI_CS_ASIZE3_bp  5  /* Address Size bit 3 position. */
4064#define EBI_CS_ASIZE4_bm  (1<<6)  /* Address Size bit 4 mask. */
4065#define EBI_CS_ASIZE4_bp  6  /* Address Size bit 4 position. */
4066
4067#define EBI_CS_MODE_gm  0x03  /* Memory Mode group mask. */
4068#define EBI_CS_MODE_gp  0  /* Memory Mode group position. */
4069#define EBI_CS_MODE0_bm  (1<<0)  /* Memory Mode bit 0 mask. */
4070#define EBI_CS_MODE0_bp  0  /* Memory Mode bit 0 position. */
4071#define EBI_CS_MODE1_bm  (1<<1)  /* Memory Mode bit 1 mask. */
4072#define EBI_CS_MODE1_bp  1  /* Memory Mode bit 1 position. */
4073
4074
4075/* EBI_CS.CTRLB  bit masks and bit positions */
4076#define EBI_CS_SRWS_gm  0x07  /* SRAM Wait State Cycles group mask. */
4077#define EBI_CS_SRWS_gp  0  /* SRAM Wait State Cycles group position. */
4078#define EBI_CS_SRWS0_bm  (1<<0)  /* SRAM Wait State Cycles bit 0 mask. */
4079#define EBI_CS_SRWS0_bp  0  /* SRAM Wait State Cycles bit 0 position. */
4080#define EBI_CS_SRWS1_bm  (1<<1)  /* SRAM Wait State Cycles bit 1 mask. */
4081#define EBI_CS_SRWS1_bp  1  /* SRAM Wait State Cycles bit 1 position. */
4082#define EBI_CS_SRWS2_bm  (1<<2)  /* SRAM Wait State Cycles bit 2 mask. */
4083#define EBI_CS_SRWS2_bp  2  /* SRAM Wait State Cycles bit 2 position. */
4084
4085#define EBI_CS_SDINITDONE_bm  0x80  /* SDRAM Initialization Done bit mask. */
4086#define EBI_CS_SDINITDONE_bp  7  /* SDRAM Initialization Done bit position. */
4087
4088#define EBI_CS_SDSREN_bm  0x04  /* SDRAM Self-refresh Enable bit mask. */
4089#define EBI_CS_SDSREN_bp  2  /* SDRAM Self-refresh Enable bit position. */
4090
4091#define EBI_CS_SDMODE_gm  0x03  /* SDRAM Mode group mask. */
4092#define EBI_CS_SDMODE_gp  0  /* SDRAM Mode group position. */
4093#define EBI_CS_SDMODE0_bm  (1<<0)  /* SDRAM Mode bit 0 mask. */
4094#define EBI_CS_SDMODE0_bp  0  /* SDRAM Mode bit 0 position. */
4095#define EBI_CS_SDMODE1_bm  (1<<1)  /* SDRAM Mode bit 1 mask. */
4096#define EBI_CS_SDMODE1_bp  1  /* SDRAM Mode bit 1 position. */
4097
4098
4099/* EBI.CTRL  bit masks and bit positions */
4100#define EBI_SDDATAW_gm  0xC0  /* SDRAM Data Width Setting group mask. */
4101#define EBI_SDDATAW_gp  6  /* SDRAM Data Width Setting group position. */
4102#define EBI_SDDATAW0_bm  (1<<6)  /* SDRAM Data Width Setting bit 0 mask. */
4103#define EBI_SDDATAW0_bp  6  /* SDRAM Data Width Setting bit 0 position. */
4104#define EBI_SDDATAW1_bm  (1<<7)  /* SDRAM Data Width Setting bit 1 mask. */
4105#define EBI_SDDATAW1_bp  7  /* SDRAM Data Width Setting bit 1 position. */
4106
4107#define EBI_LPCMODE_gm  0x30  /* SRAM LPC Mode group mask. */
4108#define EBI_LPCMODE_gp  4  /* SRAM LPC Mode group position. */
4109#define EBI_LPCMODE0_bm  (1<<4)  /* SRAM LPC Mode bit 0 mask. */
4110#define EBI_LPCMODE0_bp  4  /* SRAM LPC Mode bit 0 position. */
4111#define EBI_LPCMODE1_bm  (1<<5)  /* SRAM LPC Mode bit 1 mask. */
4112#define EBI_LPCMODE1_bp  5  /* SRAM LPC Mode bit 1 position. */
4113
4114#define EBI_SRMODE_gm  0x0C  /* SRAM Mode group mask. */
4115#define EBI_SRMODE_gp  2  /* SRAM Mode group position. */
4116#define EBI_SRMODE0_bm  (1<<2)  /* SRAM Mode bit 0 mask. */
4117#define EBI_SRMODE0_bp  2  /* SRAM Mode bit 0 position. */
4118#define EBI_SRMODE1_bm  (1<<3)  /* SRAM Mode bit 1 mask. */
4119#define EBI_SRMODE1_bp  3  /* SRAM Mode bit 1 position. */
4120
4121#define EBI_IFMODE_gm  0x03  /* Interface Mode group mask. */
4122#define EBI_IFMODE_gp  0  /* Interface Mode group position. */
4123#define EBI_IFMODE0_bm  (1<<0)  /* Interface Mode bit 0 mask. */
4124#define EBI_IFMODE0_bp  0  /* Interface Mode bit 0 position. */
4125#define EBI_IFMODE1_bm  (1<<1)  /* Interface Mode bit 1 mask. */
4126#define EBI_IFMODE1_bp  1  /* Interface Mode bit 1 position. */
4127
4128
4129/* EBI.SDRAMCTRLA  bit masks and bit positions */
4130#define EBI_SDCAS_bm  0x08  /* SDRAM CAS Latency Setting bit mask. */
4131#define EBI_SDCAS_bp  3  /* SDRAM CAS Latency Setting bit position. */
4132
4133#define EBI_SDROW_bm  0x04  /* SDRAM ROW Bits Setting bit mask. */
4134#define EBI_SDROW_bp  2  /* SDRAM ROW Bits Setting bit position. */
4135
4136#define EBI_SDCOL_gm  0x03  /* SDRAM Column Bits Setting group mask. */
4137#define EBI_SDCOL_gp  0  /* SDRAM Column Bits Setting group position. */
4138#define EBI_SDCOL0_bm  (1<<0)  /* SDRAM Column Bits Setting bit 0 mask. */
4139#define EBI_SDCOL0_bp  0  /* SDRAM Column Bits Setting bit 0 position. */
4140#define EBI_SDCOL1_bm  (1<<1)  /* SDRAM Column Bits Setting bit 1 mask. */
4141#define EBI_SDCOL1_bp  1  /* SDRAM Column Bits Setting bit 1 position. */
4142
4143
4144/* EBI.SDRAMCTRLB  bit masks and bit positions */
4145#define EBI_MRDLY_gm  0xC0  /* SDRAM Mode Register Delay group mask. */
4146#define EBI_MRDLY_gp  6  /* SDRAM Mode Register Delay group position. */
4147#define EBI_MRDLY0_bm  (1<<6)  /* SDRAM Mode Register Delay bit 0 mask. */
4148#define EBI_MRDLY0_bp  6  /* SDRAM Mode Register Delay bit 0 position. */
4149#define EBI_MRDLY1_bm  (1<<7)  /* SDRAM Mode Register Delay bit 1 mask. */
4150#define EBI_MRDLY1_bp  7  /* SDRAM Mode Register Delay bit 1 position. */
4151
4152#define EBI_ROWCYCDLY_gm  0x38  /* SDRAM Row Cycle Delay group mask. */
4153#define EBI_ROWCYCDLY_gp  3  /* SDRAM Row Cycle Delay group position. */
4154#define EBI_ROWCYCDLY0_bm  (1<<3)  /* SDRAM Row Cycle Delay bit 0 mask. */
4155#define EBI_ROWCYCDLY0_bp  3  /* SDRAM Row Cycle Delay bit 0 position. */
4156#define EBI_ROWCYCDLY1_bm  (1<<4)  /* SDRAM Row Cycle Delay bit 1 mask. */
4157#define EBI_ROWCYCDLY1_bp  4  /* SDRAM Row Cycle Delay bit 1 position. */
4158#define EBI_ROWCYCDLY2_bm  (1<<5)  /* SDRAM Row Cycle Delay bit 2 mask. */
4159#define EBI_ROWCYCDLY2_bp  5  /* SDRAM Row Cycle Delay bit 2 position. */
4160
4161#define EBI_RPDLY_gm  0x07  /* SDRAM Row-to-Precharge Delay group mask. */
4162#define EBI_RPDLY_gp  0  /* SDRAM Row-to-Precharge Delay group position. */
4163#define EBI_RPDLY0_bm  (1<<0)  /* SDRAM Row-to-Precharge Delay bit 0 mask. */
4164#define EBI_RPDLY0_bp  0  /* SDRAM Row-to-Precharge Delay bit 0 position. */
4165#define EBI_RPDLY1_bm  (1<<1)  /* SDRAM Row-to-Precharge Delay bit 1 mask. */
4166#define EBI_RPDLY1_bp  1  /* SDRAM Row-to-Precharge Delay bit 1 position. */
4167#define EBI_RPDLY2_bm  (1<<2)  /* SDRAM Row-to-Precharge Delay bit 2 mask. */
4168#define EBI_RPDLY2_bp  2  /* SDRAM Row-to-Precharge Delay bit 2 position. */
4169
4170
4171/* EBI.SDRAMCTRLC  bit masks and bit positions */
4172#define EBI_WRDLY_gm  0xC0  /* SDRAM Write Recovery Delay group mask. */
4173#define EBI_WRDLY_gp  6  /* SDRAM Write Recovery Delay group position. */
4174#define EBI_WRDLY0_bm  (1<<6)  /* SDRAM Write Recovery Delay bit 0 mask. */
4175#define EBI_WRDLY0_bp  6  /* SDRAM Write Recovery Delay bit 0 position. */
4176#define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
4177#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
4178
4179#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
4180#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
4181#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
4182#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
4183#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
4184#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
4185#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
4186#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
4187
4188#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
4189#define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
4190#define EBI_ROWCOLDLY0_bm  (1<<0)  /* SDRAM Row-to-Column Delay bit 0 mask. */
4191#define EBI_ROWCOLDLY0_bp  0  /* SDRAM Row-to-Column Delay bit 0 position. */
4192#define EBI_ROWCOLDLY1_bm  (1<<1)  /* SDRAM Row-to-Column Delay bit 1 mask. */
4193#define EBI_ROWCOLDLY1_bp  1  /* SDRAM Row-to-Column Delay bit 1 position. */
4194#define EBI_ROWCOLDLY2_bm  (1<<2)  /* SDRAM Row-to-Column Delay bit 2 mask. */
4195#define EBI_ROWCOLDLY2_bp  2  /* SDRAM Row-to-Column Delay bit 2 position. */
4196
4197
4198/* TWI - Two-Wire Interface */
4199/* TWI_MASTER.CTRLA  bit masks and bit positions */
4200#define TWI_MASTER_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
4201#define TWI_MASTER_INTLVL_gp  6  /* Interrupt Level group position. */
4202#define TWI_MASTER_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
4203#define TWI_MASTER_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
4204#define TWI_MASTER_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
4205#define TWI_MASTER_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
4206
4207#define TWI_MASTER_RIEN_bm  0x20  /* Read Interrupt Enable bit mask. */
4208#define TWI_MASTER_RIEN_bp  5  /* Read Interrupt Enable bit position. */
4209
4210#define TWI_MASTER_WIEN_bm  0x10  /* Write Interrupt Enable bit mask. */
4211#define TWI_MASTER_WIEN_bp  4  /* Write Interrupt Enable bit position. */
4212
4213#define TWI_MASTER_ENABLE_bm  0x08  /* Enable TWI Master bit mask. */
4214#define TWI_MASTER_ENABLE_bp  3  /* Enable TWI Master bit position. */
4215
4216
4217/* TWI_MASTER.CTRLB  bit masks and bit positions */
4218#define TWI_MASTER_TIMEOUT_gm  0x0C  /* Inactive Bus Timeout group mask. */
4219#define TWI_MASTER_TIMEOUT_gp  2  /* Inactive Bus Timeout group position. */
4220#define TWI_MASTER_TIMEOUT0_bm  (1<<2)  /* Inactive Bus Timeout bit 0 mask. */
4221#define TWI_MASTER_TIMEOUT0_bp  2  /* Inactive Bus Timeout bit 0 position. */
4222#define TWI_MASTER_TIMEOUT1_bm  (1<<3)  /* Inactive Bus Timeout bit 1 mask. */
4223#define TWI_MASTER_TIMEOUT1_bp  3  /* Inactive Bus Timeout bit 1 position. */
4224
4225#define TWI_MASTER_QCEN_bm  0x02  /* Quick Command Enable bit mask. */
4226#define TWI_MASTER_QCEN_bp  1  /* Quick Command Enable bit position. */
4227
4228#define TWI_MASTER_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
4229#define TWI_MASTER_SMEN_bp  0  /* Smart Mode Enable bit position. */
4230
4231
4232/* TWI_MASTER.CTRLC  bit masks and bit positions */
4233#define TWI_MASTER_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
4234#define TWI_MASTER_ACKACT_bp  2  /* Acknowledge Action bit position. */
4235
4236#define TWI_MASTER_CMD_gm  0x03  /* Command group mask. */
4237#define TWI_MASTER_CMD_gp  0  /* Command group position. */
4238#define TWI_MASTER_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
4239#define TWI_MASTER_CMD0_bp  0  /* Command bit 0 position. */
4240#define TWI_MASTER_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
4241#define TWI_MASTER_CMD1_bp  1  /* Command bit 1 position. */
4242
4243
4244/* TWI_MASTER.STATUS  bit masks and bit positions */
4245#define TWI_MASTER_RIF_bm  0x80  /* Read Interrupt Flag bit mask. */
4246#define TWI_MASTER_RIF_bp  7  /* Read Interrupt Flag bit position. */
4247
4248#define TWI_MASTER_WIF_bm  0x40  /* Write Interrupt Flag bit mask. */
4249#define TWI_MASTER_WIF_bp  6  /* Write Interrupt Flag bit position. */
4250
4251#define TWI_MASTER_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4252#define TWI_MASTER_CLKHOLD_bp  5  /* Clock Hold bit position. */
4253
4254#define TWI_MASTER_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4255#define TWI_MASTER_RXACK_bp  4  /* Received Acknowledge bit position. */
4256
4257#define TWI_MASTER_ARBLOST_bm  0x08  /* Arbitration Lost bit mask. */
4258#define TWI_MASTER_ARBLOST_bp  3  /* Arbitration Lost bit position. */
4259
4260#define TWI_MASTER_BUSERR_bm  0x04  /* Bus Error bit mask. */
4261#define TWI_MASTER_BUSERR_bp  2  /* Bus Error bit position. */
4262
4263#define TWI_MASTER_BUSSTATE_gm  0x03  /* Bus State group mask. */
4264#define TWI_MASTER_BUSSTATE_gp  0  /* Bus State group position. */
4265#define TWI_MASTER_BUSSTATE0_bm  (1<<0)  /* Bus State bit 0 mask. */
4266#define TWI_MASTER_BUSSTATE0_bp  0  /* Bus State bit 0 position. */
4267#define TWI_MASTER_BUSSTATE1_bm  (1<<1)  /* Bus State bit 1 mask. */
4268#define TWI_MASTER_BUSSTATE1_bp  1  /* Bus State bit 1 position. */
4269
4270
4271/* TWI_SLAVE.CTRLA  bit masks and bit positions */
4272#define TWI_SLAVE_INTLVL_gm  0xC0  /* Interrupt Level group mask. */
4273#define TWI_SLAVE_INTLVL_gp  6  /* Interrupt Level group position. */
4274#define TWI_SLAVE_INTLVL0_bm  (1<<6)  /* Interrupt Level bit 0 mask. */
4275#define TWI_SLAVE_INTLVL0_bp  6  /* Interrupt Level bit 0 position. */
4276#define TWI_SLAVE_INTLVL1_bm  (1<<7)  /* Interrupt Level bit 1 mask. */
4277#define TWI_SLAVE_INTLVL1_bp  7  /* Interrupt Level bit 1 position. */
4278
4279#define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
4280#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
4281
4282#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
4283#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
4284
4285#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
4286#define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
4287
4288#define TWI_SLAVE_PIEN_bm  0x04  /* Stop Interrupt Enable bit mask. */
4289#define TWI_SLAVE_PIEN_bp  2  /* Stop Interrupt Enable bit position. */
4290
4291#define TWI_SLAVE_PMEN_bm  0x02  /* Promiscuous Mode Enable bit mask. */
4292#define TWI_SLAVE_PMEN_bp  1  /* Promiscuous Mode Enable bit position. */
4293
4294#define TWI_SLAVE_SMEN_bm  0x01  /* Smart Mode Enable bit mask. */
4295#define TWI_SLAVE_SMEN_bp  0  /* Smart Mode Enable bit position. */
4296
4297
4298/* TWI_SLAVE.CTRLB  bit masks and bit positions */
4299#define TWI_SLAVE_ACKACT_bm  0x04  /* Acknowledge Action bit mask. */
4300#define TWI_SLAVE_ACKACT_bp  2  /* Acknowledge Action bit position. */
4301
4302#define TWI_SLAVE_CMD_gm  0x03  /* Command group mask. */
4303#define TWI_SLAVE_CMD_gp  0  /* Command group position. */
4304#define TWI_SLAVE_CMD0_bm  (1<<0)  /* Command bit 0 mask. */
4305#define TWI_SLAVE_CMD0_bp  0  /* Command bit 0 position. */
4306#define TWI_SLAVE_CMD1_bm  (1<<1)  /* Command bit 1 mask. */
4307#define TWI_SLAVE_CMD1_bp  1  /* Command bit 1 position. */
4308
4309
4310/* TWI_SLAVE.STATUS  bit masks and bit positions */
4311#define TWI_SLAVE_DIF_bm  0x80  /* Data Interrupt Flag bit mask. */
4312#define TWI_SLAVE_DIF_bp  7  /* Data Interrupt Flag bit position. */
4313
4314#define TWI_SLAVE_APIF_bm  0x40  /* Address/Stop Interrupt Flag bit mask. */
4315#define TWI_SLAVE_APIF_bp  6  /* Address/Stop Interrupt Flag bit position. */
4316
4317#define TWI_SLAVE_CLKHOLD_bm  0x20  /* Clock Hold bit mask. */
4318#define TWI_SLAVE_CLKHOLD_bp  5  /* Clock Hold bit position. */
4319
4320#define TWI_SLAVE_RXACK_bm  0x10  /* Received Acknowledge bit mask. */
4321#define TWI_SLAVE_RXACK_bp  4  /* Received Acknowledge bit position. */
4322
4323#define TWI_SLAVE_COLL_bm  0x08  /* Collision bit mask. */
4324#define TWI_SLAVE_COLL_bp  3  /* Collision bit position. */
4325
4326#define TWI_SLAVE_BUSERR_bm  0x04  /* Bus Error bit mask. */
4327#define TWI_SLAVE_BUSERR_bp  2  /* Bus Error bit position. */
4328
4329#define TWI_SLAVE_DIR_bm  0x02  /* Read/Write Direction bit mask. */
4330#define TWI_SLAVE_DIR_bp  1  /* Read/Write Direction bit position. */
4331
4332#define TWI_SLAVE_AP_bm  0x01  /* Slave Address or Stop bit mask. */
4333#define TWI_SLAVE_AP_bp  0  /* Slave Address or Stop bit position. */
4334
4335
4336/* TWI_SLAVE.ADDRMASK  bit masks and bit positions */
4337#define TWI_SLAVE_ADDRMASK_gm  0xFE  /* Address Mask group mask. */
4338#define TWI_SLAVE_ADDRMASK_gp  1  /* Address Mask group position. */
4339#define TWI_SLAVE_ADDRMASK0_bm  (1<<1)  /* Address Mask bit 0 mask. */
4340#define TWI_SLAVE_ADDRMASK0_bp  1  /* Address Mask bit 0 position. */
4341#define TWI_SLAVE_ADDRMASK1_bm  (1<<2)  /* Address Mask bit 1 mask. */
4342#define TWI_SLAVE_ADDRMASK1_bp  2  /* Address Mask bit 1 position. */
4343#define TWI_SLAVE_ADDRMASK2_bm  (1<<3)  /* Address Mask bit 2 mask. */
4344#define TWI_SLAVE_ADDRMASK2_bp  3  /* Address Mask bit 2 position. */
4345#define TWI_SLAVE_ADDRMASK3_bm  (1<<4)  /* Address Mask bit 3 mask. */
4346#define TWI_SLAVE_ADDRMASK3_bp  4  /* Address Mask bit 3 position. */
4347#define TWI_SLAVE_ADDRMASK4_bm  (1<<5)  /* Address Mask bit 4 mask. */
4348#define TWI_SLAVE_ADDRMASK4_bp  5  /* Address Mask bit 4 position. */
4349#define TWI_SLAVE_ADDRMASK5_bm  (1<<6)  /* Address Mask bit 5 mask. */
4350#define TWI_SLAVE_ADDRMASK5_bp  6  /* Address Mask bit 5 position. */
4351#define TWI_SLAVE_ADDRMASK6_bm  (1<<7)  /* Address Mask bit 6 mask. */
4352#define TWI_SLAVE_ADDRMASK6_bp  7  /* Address Mask bit 6 position. */
4353
4354#define TWI_SLAVE_ADDREN_bm  0x01  /* Address Enable bit mask. */
4355#define TWI_SLAVE_ADDREN_bp  0  /* Address Enable bit position. */
4356
4357
4358/* TWI.CTRL  bit masks and bit positions */
4359#define TWI_SDAHOLD_bm  0x02  /* SDA Hold Time Enable bit mask. */
4360#define TWI_SDAHOLD_bp  1  /* SDA Hold Time Enable bit position. */
4361
4362#define TWI_EDIEN_bm  0x01  /* External Driver Interface Enable bit mask. */
4363#define TWI_EDIEN_bp  0  /* External Driver Interface Enable bit position. */
4364
4365
4366/* PORT - Port Configuration */
4367/* PORTCFG.VPCTRLA  bit masks and bit positions */
4368#define PORTCFG_VP1MAP_gm  0xF0  /* Virtual Port 1 Mapping group mask. */
4369#define PORTCFG_VP1MAP_gp  4  /* Virtual Port 1 Mapping group position. */
4370#define PORTCFG_VP1MAP0_bm  (1<<4)  /* Virtual Port 1 Mapping bit 0 mask. */
4371#define PORTCFG_VP1MAP0_bp  4  /* Virtual Port 1 Mapping bit 0 position. */
4372#define PORTCFG_VP1MAP1_bm  (1<<5)  /* Virtual Port 1 Mapping bit 1 mask. */
4373#define PORTCFG_VP1MAP1_bp  5  /* Virtual Port 1 Mapping bit 1 position. */
4374#define PORTCFG_VP1MAP2_bm  (1<<6)  /* Virtual Port 1 Mapping bit 2 mask. */
4375#define PORTCFG_VP1MAP2_bp  6  /* Virtual Port 1 Mapping bit 2 position. */
4376#define PORTCFG_VP1MAP3_bm  (1<<7)  /* Virtual Port 1 Mapping bit 3 mask. */
4377#define PORTCFG_VP1MAP3_bp  7  /* Virtual Port 1 Mapping bit 3 position. */
4378
4379#define PORTCFG_VP0MAP_gm  0x0F  /* Virtual Port 0 Mapping group mask. */
4380#define PORTCFG_VP0MAP_gp  0  /* Virtual Port 0 Mapping group position. */
4381#define PORTCFG_VP0MAP0_bm  (1<<0)  /* Virtual Port 0 Mapping bit 0 mask. */
4382#define PORTCFG_VP0MAP0_bp  0  /* Virtual Port 0 Mapping bit 0 position. */
4383#define PORTCFG_VP0MAP1_bm  (1<<1)  /* Virtual Port 0 Mapping bit 1 mask. */
4384#define PORTCFG_VP0MAP1_bp  1  /* Virtual Port 0 Mapping bit 1 position. */
4385#define PORTCFG_VP0MAP2_bm  (1<<2)  /* Virtual Port 0 Mapping bit 2 mask. */
4386#define PORTCFG_VP0MAP2_bp  2  /* Virtual Port 0 Mapping bit 2 position. */
4387#define PORTCFG_VP0MAP3_bm  (1<<3)  /* Virtual Port 0 Mapping bit 3 mask. */
4388#define PORTCFG_VP0MAP3_bp  3  /* Virtual Port 0 Mapping bit 3 position. */
4389
4390
4391/* PORTCFG.VPCTRLB  bit masks and bit positions */
4392#define PORTCFG_VP3MAP_gm  0xF0  /* Virtual Port 3 Mapping group mask. */
4393#define PORTCFG_VP3MAP_gp  4  /* Virtual Port 3 Mapping group position. */
4394#define PORTCFG_VP3MAP0_bm  (1<<4)  /* Virtual Port 3 Mapping bit 0 mask. */
4395#define PORTCFG_VP3MAP0_bp  4  /* Virtual Port 3 Mapping bit 0 position. */
4396#define PORTCFG_VP3MAP1_bm  (1<<5)  /* Virtual Port 3 Mapping bit 1 mask. */
4397#define PORTCFG_VP3MAP1_bp  5  /* Virtual Port 3 Mapping bit 1 position. */
4398#define PORTCFG_VP3MAP2_bm  (1<<6)  /* Virtual Port 3 Mapping bit 2 mask. */
4399#define PORTCFG_VP3MAP2_bp  6  /* Virtual Port 3 Mapping bit 2 position. */
4400#define PORTCFG_VP3MAP3_bm  (1<<7)  /* Virtual Port 3 Mapping bit 3 mask. */
4401#define PORTCFG_VP3MAP3_bp  7  /* Virtual Port 3 Mapping bit 3 position. */
4402
4403#define PORTCFG_VP2MAP_gm  0x0F  /* Virtual Port 2 Mapping group mask. */
4404#define PORTCFG_VP2MAP_gp  0  /* Virtual Port 2 Mapping group position. */
4405#define PORTCFG_VP2MAP0_bm  (1<<0)  /* Virtual Port 2 Mapping bit 0 mask. */
4406#define PORTCFG_VP2MAP0_bp  0  /* Virtual Port 2 Mapping bit 0 position. */
4407#define PORTCFG_VP2MAP1_bm  (1<<1)  /* Virtual Port 2 Mapping bit 1 mask. */
4408#define PORTCFG_VP2MAP1_bp  1  /* Virtual Port 2 Mapping bit 1 position. */
4409#define PORTCFG_VP2MAP2_bm  (1<<2)  /* Virtual Port 2 Mapping bit 2 mask. */
4410#define PORTCFG_VP2MAP2_bp  2  /* Virtual Port 2 Mapping bit 2 position. */
4411#define PORTCFG_VP2MAP3_bm  (1<<3)  /* Virtual Port 2 Mapping bit 3 mask. */
4412#define PORTCFG_VP2MAP3_bp  3  /* Virtual Port 2 Mapping bit 3 position. */
4413
4414
4415/* PORTCFG.CLKEVOUT  bit masks and bit positions */
4416#define PORTCFG_CLKOUT_gm  0x03  /* Clock Output Port group mask. */
4417#define PORTCFG_CLKOUT_gp  0  /* Clock Output Port group position. */
4418#define PORTCFG_CLKOUT0_bm  (1<<0)  /* Clock Output Port bit 0 mask. */
4419#define PORTCFG_CLKOUT0_bp  0  /* Clock Output Port bit 0 position. */
4420#define PORTCFG_CLKOUT1_bm  (1<<1)  /* Clock Output Port bit 1 mask. */
4421#define PORTCFG_CLKOUT1_bp  1  /* Clock Output Port bit 1 position. */
4422
4423#define PORTCFG_EVOUT_gm  0x30  /* Event Output Port group mask. */
4424#define PORTCFG_EVOUT_gp  4  /* Event Output Port group position. */
4425#define PORTCFG_EVOUT0_bm  (1<<4)  /* Event Output Port bit 0 mask. */
4426#define PORTCFG_EVOUT0_bp  4  /* Event Output Port bit 0 position. */
4427#define PORTCFG_EVOUT1_bm  (1<<5)  /* Event Output Port bit 1 mask. */
4428#define PORTCFG_EVOUT1_bp  5  /* Event Output Port bit 1 position. */
4429
4430
4431/* VPORT.INTFLAGS  bit masks and bit positions */
4432#define VPORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4433#define VPORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4434
4435#define VPORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4436#define VPORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4437
4438
4439/* PORT.INTCTRL  bit masks and bit positions */
4440#define PORT_INT1LVL_gm  0x0C  /* Port Interrupt 1 Level group mask. */
4441#define PORT_INT1LVL_gp  2  /* Port Interrupt 1 Level group position. */
4442#define PORT_INT1LVL0_bm  (1<<2)  /* Port Interrupt 1 Level bit 0 mask. */
4443#define PORT_INT1LVL0_bp  2  /* Port Interrupt 1 Level bit 0 position. */
4444#define PORT_INT1LVL1_bm  (1<<3)  /* Port Interrupt 1 Level bit 1 mask. */
4445#define PORT_INT1LVL1_bp  3  /* Port Interrupt 1 Level bit 1 position. */
4446
4447#define PORT_INT0LVL_gm  0x03  /* Port Interrupt 0 Level group mask. */
4448#define PORT_INT0LVL_gp  0  /* Port Interrupt 0 Level group position. */
4449#define PORT_INT0LVL0_bm  (1<<0)  /* Port Interrupt 0 Level bit 0 mask. */
4450#define PORT_INT0LVL0_bp  0  /* Port Interrupt 0 Level bit 0 position. */
4451#define PORT_INT0LVL1_bm  (1<<1)  /* Port Interrupt 0 Level bit 1 mask. */
4452#define PORT_INT0LVL1_bp  1  /* Port Interrupt 0 Level bit 1 position. */
4453
4454
4455/* PORT.INTFLAGS  bit masks and bit positions */
4456#define PORT_INT1IF_bm  0x02  /* Port Interrupt 1 Flag bit mask. */
4457#define PORT_INT1IF_bp  1  /* Port Interrupt 1 Flag bit position. */
4458
4459#define PORT_INT0IF_bm  0x01  /* Port Interrupt 0 Flag bit mask. */
4460#define PORT_INT0IF_bp  0  /* Port Interrupt 0 Flag bit position. */
4461
4462
4463/* PORT.PIN0CTRL  bit masks and bit positions */
4464#define PORT_SRLEN_bm  0x80  /* Slew Rate Enable bit mask. */
4465#define PORT_SRLEN_bp  7  /* Slew Rate Enable bit position. */
4466
4467#define PORT_INVEN_bm  0x40  /* Inverted I/O Enable bit mask. */
4468#define PORT_INVEN_bp  6  /* Inverted I/O Enable bit position. */
4469
4470#define PORT_OPC_gm  0x38  /* Output/Pull Configuration group mask. */
4471#define PORT_OPC_gp  3  /* Output/Pull Configuration group position. */
4472#define PORT_OPC0_bm  (1<<3)  /* Output/Pull Configuration bit 0 mask. */
4473#define PORT_OPC0_bp  3  /* Output/Pull Configuration bit 0 position. */
4474#define PORT_OPC1_bm  (1<<4)  /* Output/Pull Configuration bit 1 mask. */
4475#define PORT_OPC1_bp  4  /* Output/Pull Configuration bit 1 position. */
4476#define PORT_OPC2_bm  (1<<5)  /* Output/Pull Configuration bit 2 mask. */
4477#define PORT_OPC2_bp  5  /* Output/Pull Configuration bit 2 position. */
4478
4479#define PORT_ISC_gm  0x07  /* Input/Sense Configuration group mask. */
4480#define PORT_ISC_gp  0  /* Input/Sense Configuration group position. */
4481#define PORT_ISC0_bm  (1<<0)  /* Input/Sense Configuration bit 0 mask. */
4482#define PORT_ISC0_bp  0  /* Input/Sense Configuration bit 0 position. */
4483#define PORT_ISC1_bm  (1<<1)  /* Input/Sense Configuration bit 1 mask. */
4484#define PORT_ISC1_bp  1  /* Input/Sense Configuration bit 1 position. */
4485#define PORT_ISC2_bm  (1<<2)  /* Input/Sense Configuration bit 2 mask. */
4486#define PORT_ISC2_bp  2  /* Input/Sense Configuration bit 2 position. */
4487
4488
4489/* PORT.PIN1CTRL  bit masks and bit positions */
4490/* PORT_SRLEN_bm  Predefined. */
4491/* PORT_SRLEN_bp  Predefined. */
4492
4493/* PORT_INVEN_bm  Predefined. */
4494/* PORT_INVEN_bp  Predefined. */
4495
4496/* PORT_OPC_gm  Predefined. */
4497/* PORT_OPC_gp  Predefined. */
4498/* PORT_OPC0_bm  Predefined. */
4499/* PORT_OPC0_bp  Predefined. */
4500/* PORT_OPC1_bm  Predefined. */
4501/* PORT_OPC1_bp  Predefined. */
4502/* PORT_OPC2_bm  Predefined. */
4503/* PORT_OPC2_bp  Predefined. */
4504
4505/* PORT_ISC_gm  Predefined. */
4506/* PORT_ISC_gp  Predefined. */
4507/* PORT_ISC0_bm  Predefined. */
4508/* PORT_ISC0_bp  Predefined. */
4509/* PORT_ISC1_bm  Predefined. */
4510/* PORT_ISC1_bp  Predefined. */
4511/* PORT_ISC2_bm  Predefined. */
4512/* PORT_ISC2_bp  Predefined. */
4513
4514
4515/* PORT.PIN2CTRL  bit masks and bit positions */
4516/* PORT_SRLEN_bm  Predefined. */
4517/* PORT_SRLEN_bp  Predefined. */
4518
4519/* PORT_INVEN_bm  Predefined. */
4520/* PORT_INVEN_bp  Predefined. */
4521
4522/* PORT_OPC_gm  Predefined. */
4523/* PORT_OPC_gp  Predefined. */
4524/* PORT_OPC0_bm  Predefined. */
4525/* PORT_OPC0_bp  Predefined. */
4526/* PORT_OPC1_bm  Predefined. */
4527/* PORT_OPC1_bp  Predefined. */
4528/* PORT_OPC2_bm  Predefined. */
4529/* PORT_OPC2_bp  Predefined. */
4530
4531/* PORT_ISC_gm  Predefined. */
4532/* PORT_ISC_gp  Predefined. */
4533/* PORT_ISC0_bm  Predefined. */
4534/* PORT_ISC0_bp  Predefined. */
4535/* PORT_ISC1_bm  Predefined. */
4536/* PORT_ISC1_bp  Predefined. */
4537/* PORT_ISC2_bm  Predefined. */
4538/* PORT_ISC2_bp  Predefined. */
4539
4540
4541/* PORT.PIN3CTRL  bit masks and bit positions */
4542/* PORT_SRLEN_bm  Predefined. */
4543/* PORT_SRLEN_bp  Predefined. */
4544
4545/* PORT_INVEN_bm  Predefined. */
4546/* PORT_INVEN_bp  Predefined. */
4547
4548/* PORT_OPC_gm  Predefined. */
4549/* PORT_OPC_gp  Predefined. */
4550/* PORT_OPC0_bm  Predefined. */
4551/* PORT_OPC0_bp  Predefined. */
4552/* PORT_OPC1_bm  Predefined. */
4553/* PORT_OPC1_bp  Predefined. */
4554/* PORT_OPC2_bm  Predefined. */
4555/* PORT_OPC2_bp  Predefined. */
4556
4557/* PORT_ISC_gm  Predefined. */
4558/* PORT_ISC_gp  Predefined. */
4559/* PORT_ISC0_bm  Predefined. */
4560/* PORT_ISC0_bp  Predefined. */
4561/* PORT_ISC1_bm  Predefined. */
4562/* PORT_ISC1_bp  Predefined. */
4563/* PORT_ISC2_bm  Predefined. */
4564/* PORT_ISC2_bp  Predefined. */
4565
4566
4567/* PORT.PIN4CTRL  bit masks and bit positions */
4568/* PORT_SRLEN_bm  Predefined. */
4569/* PORT_SRLEN_bp  Predefined. */
4570
4571/* PORT_INVEN_bm  Predefined. */
4572/* PORT_INVEN_bp  Predefined. */
4573
4574/* PORT_OPC_gm  Predefined. */
4575/* PORT_OPC_gp  Predefined. */
4576/* PORT_OPC0_bm  Predefined. */
4577/* PORT_OPC0_bp  Predefined. */
4578/* PORT_OPC1_bm  Predefined. */
4579/* PORT_OPC1_bp  Predefined. */
4580/* PORT_OPC2_bm  Predefined. */
4581/* PORT_OPC2_bp  Predefined. */
4582
4583/* PORT_ISC_gm  Predefined. */
4584/* PORT_ISC_gp  Predefined. */
4585/* PORT_ISC0_bm  Predefined. */
4586/* PORT_ISC0_bp  Predefined. */
4587/* PORT_ISC1_bm  Predefined. */
4588/* PORT_ISC1_bp  Predefined. */
4589/* PORT_ISC2_bm  Predefined. */
4590/* PORT_ISC2_bp  Predefined. */
4591
4592
4593/* PORT.PIN5CTRL  bit masks and bit positions */
4594/* PORT_SRLEN_bm  Predefined. */
4595/* PORT_SRLEN_bp  Predefined. */
4596
4597/* PORT_INVEN_bm  Predefined. */
4598/* PORT_INVEN_bp  Predefined. */
4599
4600/* PORT_OPC_gm  Predefined. */
4601/* PORT_OPC_gp  Predefined. */
4602/* PORT_OPC0_bm  Predefined. */
4603/* PORT_OPC0_bp  Predefined. */
4604/* PORT_OPC1_bm  Predefined. */
4605/* PORT_OPC1_bp  Predefined. */
4606/* PORT_OPC2_bm  Predefined. */
4607/* PORT_OPC2_bp  Predefined. */
4608
4609/* PORT_ISC_gm  Predefined. */
4610/* PORT_ISC_gp  Predefined. */
4611/* PORT_ISC0_bm  Predefined. */
4612/* PORT_ISC0_bp  Predefined. */
4613/* PORT_ISC1_bm  Predefined. */
4614/* PORT_ISC1_bp  Predefined. */
4615/* PORT_ISC2_bm  Predefined. */
4616/* PORT_ISC2_bp  Predefined. */
4617
4618
4619/* PORT.PIN6CTRL  bit masks and bit positions */
4620/* PORT_SRLEN_bm  Predefined. */
4621/* PORT_SRLEN_bp  Predefined. */
4622
4623/* PORT_INVEN_bm  Predefined. */
4624/* PORT_INVEN_bp  Predefined. */
4625
4626/* PORT_OPC_gm  Predefined. */
4627/* PORT_OPC_gp  Predefined. */
4628/* PORT_OPC0_bm  Predefined. */
4629/* PORT_OPC0_bp  Predefined. */
4630/* PORT_OPC1_bm  Predefined. */
4631/* PORT_OPC1_bp  Predefined. */
4632/* PORT_OPC2_bm  Predefined. */
4633/* PORT_OPC2_bp  Predefined. */
4634
4635/* PORT_ISC_gm  Predefined. */
4636/* PORT_ISC_gp  Predefined. */
4637/* PORT_ISC0_bm  Predefined. */
4638/* PORT_ISC0_bp  Predefined. */
4639/* PORT_ISC1_bm  Predefined. */
4640/* PORT_ISC1_bp  Predefined. */
4641/* PORT_ISC2_bm  Predefined. */
4642/* PORT_ISC2_bp  Predefined. */
4643
4644
4645/* PORT.PIN7CTRL  bit masks and bit positions */
4646/* PORT_SRLEN_bm  Predefined. */
4647/* PORT_SRLEN_bp  Predefined. */
4648
4649/* PORT_INVEN_bm  Predefined. */
4650/* PORT_INVEN_bp  Predefined. */
4651
4652/* PORT_OPC_gm  Predefined. */
4653/* PORT_OPC_gp  Predefined. */
4654/* PORT_OPC0_bm  Predefined. */
4655/* PORT_OPC0_bp  Predefined. */
4656/* PORT_OPC1_bm  Predefined. */
4657/* PORT_OPC1_bp  Predefined. */
4658/* PORT_OPC2_bm  Predefined. */
4659/* PORT_OPC2_bp  Predefined. */
4660
4661/* PORT_ISC_gm  Predefined. */
4662/* PORT_ISC_gp  Predefined. */
4663/* PORT_ISC0_bm  Predefined. */
4664/* PORT_ISC0_bp  Predefined. */
4665/* PORT_ISC1_bm  Predefined. */
4666/* PORT_ISC1_bp  Predefined. */
4667/* PORT_ISC2_bm  Predefined. */
4668/* PORT_ISC2_bp  Predefined. */
4669
4670
4671/* TC - 16-bit Timer/Counter With PWM */
4672/* TC0.CTRLA  bit masks and bit positions */
4673#define TC0_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4674#define TC0_CLKSEL_gp  0  /* Clock Selection group position. */
4675#define TC0_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4676#define TC0_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4677#define TC0_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4678#define TC0_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4679#define TC0_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4680#define TC0_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4681#define TC0_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4682#define TC0_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4683
4684
4685/* TC0.CTRLB  bit masks and bit positions */
4686#define TC0_CCDEN_bm  0x80  /* Compare or Capture D Enable bit mask. */
4687#define TC0_CCDEN_bp  7  /* Compare or Capture D Enable bit position. */
4688
4689#define TC0_CCCEN_bm  0x40  /* Compare or Capture C Enable bit mask. */
4690#define TC0_CCCEN_bp  6  /* Compare or Capture C Enable bit position. */
4691
4692#define TC0_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4693#define TC0_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4694
4695#define TC0_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4696#define TC0_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4697
4698#define TC0_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4699#define TC0_WGMODE_gp  0  /* Waveform generation mode group position. */
4700#define TC0_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4701#define TC0_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4702#define TC0_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4703#define TC0_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4704#define TC0_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4705#define TC0_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4706
4707
4708/* TC0.CTRLC  bit masks and bit positions */
4709#define TC0_CMPD_bm  0x08  /* Compare D Output Value bit mask. */
4710#define TC0_CMPD_bp  3  /* Compare D Output Value bit position. */
4711
4712#define TC0_CMPC_bm  0x04  /* Compare C Output Value bit mask. */
4713#define TC0_CMPC_bp  2  /* Compare C Output Value bit position. */
4714
4715#define TC0_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4716#define TC0_CMPB_bp  1  /* Compare B Output Value bit position. */
4717
4718#define TC0_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4719#define TC0_CMPA_bp  0  /* Compare A Output Value bit position. */
4720
4721
4722/* TC0.CTRLD  bit masks and bit positions */
4723#define TC0_EVACT_gm  0xE0  /* Event Action group mask. */
4724#define TC0_EVACT_gp  5  /* Event Action group position. */
4725#define TC0_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4726#define TC0_EVACT0_bp  5  /* Event Action bit 0 position. */
4727#define TC0_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4728#define TC0_EVACT1_bp  6  /* Event Action bit 1 position. */
4729#define TC0_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4730#define TC0_EVACT2_bp  7  /* Event Action bit 2 position. */
4731
4732#define TC0_EVDLY_bm  0x10  /* Event Delay bit mask. */
4733#define TC0_EVDLY_bp  4  /* Event Delay bit position. */
4734
4735#define TC0_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4736#define TC0_EVSEL_gp  0  /* Event Source Select group position. */
4737#define TC0_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4738#define TC0_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4739#define TC0_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4740#define TC0_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4741#define TC0_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4742#define TC0_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4743#define TC0_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4744#define TC0_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4745
4746
4747/* TC0.CTRLE  bit masks and bit positions */
4748#define TC0_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
4749#define TC0_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
4750
4751#define TC0_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4752#define TC0_BYTEM_bp  0  /* Byte Mode bit position. */
4753
4754
4755/* TC0.INTCTRLA  bit masks and bit positions */
4756#define TC0_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4757#define TC0_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4758#define TC0_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4759#define TC0_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4760#define TC0_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4761#define TC0_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4762
4763#define TC0_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4764#define TC0_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4765#define TC0_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4766#define TC0_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4767#define TC0_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4768#define TC0_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4769
4770
4771/* TC0.INTCTRLB  bit masks and bit positions */
4772#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
4773#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
4774#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
4775#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
4776#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
4777#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
4778
4779#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
4780#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
4781#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
4782#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
4783#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
4784#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
4785
4786#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4787#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4788#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4789#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4790#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4791#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4792
4793#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4794#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4795#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4796#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4797#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4798#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4799
4800
4801/* TC0.CTRLFCLR  bit masks and bit positions */
4802#define TC0_CMD_gm  0x0C  /* Command group mask. */
4803#define TC0_CMD_gp  2  /* Command group position. */
4804#define TC0_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4805#define TC0_CMD0_bp  2  /* Command bit 0 position. */
4806#define TC0_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4807#define TC0_CMD1_bp  3  /* Command bit 1 position. */
4808
4809#define TC0_LUPD_bm  0x02  /* Lock Update bit mask. */
4810#define TC0_LUPD_bp  1  /* Lock Update bit position. */
4811
4812#define TC0_DIR_bm  0x01  /* Direction bit mask. */
4813#define TC0_DIR_bp  0  /* Direction bit position. */
4814
4815
4816/* TC0.CTRLFSET  bit masks and bit positions */
4817/* TC0_CMD_gm  Predefined. */
4818/* TC0_CMD_gp  Predefined. */
4819/* TC0_CMD0_bm  Predefined. */
4820/* TC0_CMD0_bp  Predefined. */
4821/* TC0_CMD1_bm  Predefined. */
4822/* TC0_CMD1_bp  Predefined. */
4823
4824/* TC0_LUPD_bm  Predefined. */
4825/* TC0_LUPD_bp  Predefined. */
4826
4827/* TC0_DIR_bm  Predefined. */
4828/* TC0_DIR_bp  Predefined. */
4829
4830
4831/* TC0.CTRLGCLR  bit masks and bit positions */
4832#define TC0_CCDBV_bm  0x10  /* Compare or Capture D Buffer Valid bit mask. */
4833#define TC0_CCDBV_bp  4  /* Compare or Capture D Buffer Valid bit position. */
4834
4835#define TC0_CCCBV_bm  0x08  /* Compare or Capture C Buffer Valid bit mask. */
4836#define TC0_CCCBV_bp  3  /* Compare or Capture C Buffer Valid bit position. */
4837
4838#define TC0_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
4839#define TC0_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
4840
4841#define TC0_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
4842#define TC0_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
4843
4844#define TC0_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
4845#define TC0_PERBV_bp  0  /* Period Buffer Valid bit position. */
4846
4847
4848/* TC0.CTRLGSET  bit masks and bit positions */
4849/* TC0_CCDBV_bm  Predefined. */
4850/* TC0_CCDBV_bp  Predefined. */
4851
4852/* TC0_CCCBV_bm  Predefined. */
4853/* TC0_CCCBV_bp  Predefined. */
4854
4855/* TC0_CCBBV_bm  Predefined. */
4856/* TC0_CCBBV_bp  Predefined. */
4857
4858/* TC0_CCABV_bm  Predefined. */
4859/* TC0_CCABV_bp  Predefined. */
4860
4861/* TC0_PERBV_bm  Predefined. */
4862/* TC0_PERBV_bp  Predefined. */
4863
4864
4865/* TC0.INTFLAGS  bit masks and bit positions */
4866#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
4867#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
4868
4869#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
4870#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
4871
4872#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
4873#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
4874
4875#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
4876#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
4877
4878#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
4879#define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
4880
4881#define TC0_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
4882#define TC0_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
4883
4884
4885/* TC1.CTRLA  bit masks and bit positions */
4886#define TC1_CLKSEL_gm  0x0F  /* Clock Selection group mask. */
4887#define TC1_CLKSEL_gp  0  /* Clock Selection group position. */
4888#define TC1_CLKSEL0_bm  (1<<0)  /* Clock Selection bit 0 mask. */
4889#define TC1_CLKSEL0_bp  0  /* Clock Selection bit 0 position. */
4890#define TC1_CLKSEL1_bm  (1<<1)  /* Clock Selection bit 1 mask. */
4891#define TC1_CLKSEL1_bp  1  /* Clock Selection bit 1 position. */
4892#define TC1_CLKSEL2_bm  (1<<2)  /* Clock Selection bit 2 mask. */
4893#define TC1_CLKSEL2_bp  2  /* Clock Selection bit 2 position. */
4894#define TC1_CLKSEL3_bm  (1<<3)  /* Clock Selection bit 3 mask. */
4895#define TC1_CLKSEL3_bp  3  /* Clock Selection bit 3 position. */
4896
4897
4898/* TC1.CTRLB  bit masks and bit positions */
4899#define TC1_CCBEN_bm  0x20  /* Compare or Capture B Enable bit mask. */
4900#define TC1_CCBEN_bp  5  /* Compare or Capture B Enable bit position. */
4901
4902#define TC1_CCAEN_bm  0x10  /* Compare or Capture A Enable bit mask. */
4903#define TC1_CCAEN_bp  4  /* Compare or Capture A Enable bit position. */
4904
4905#define TC1_WGMODE_gm  0x07  /* Waveform generation mode group mask. */
4906#define TC1_WGMODE_gp  0  /* Waveform generation mode group position. */
4907#define TC1_WGMODE0_bm  (1<<0)  /* Waveform generation mode bit 0 mask. */
4908#define TC1_WGMODE0_bp  0  /* Waveform generation mode bit 0 position. */
4909#define TC1_WGMODE1_bm  (1<<1)  /* Waveform generation mode bit 1 mask. */
4910#define TC1_WGMODE1_bp  1  /* Waveform generation mode bit 1 position. */
4911#define TC1_WGMODE2_bm  (1<<2)  /* Waveform generation mode bit 2 mask. */
4912#define TC1_WGMODE2_bp  2  /* Waveform generation mode bit 2 position. */
4913
4914
4915/* TC1.CTRLC  bit masks and bit positions */
4916#define TC1_CMPB_bm  0x02  /* Compare B Output Value bit mask. */
4917#define TC1_CMPB_bp  1  /* Compare B Output Value bit position. */
4918
4919#define TC1_CMPA_bm  0x01  /* Compare A Output Value bit mask. */
4920#define TC1_CMPA_bp  0  /* Compare A Output Value bit position. */
4921
4922
4923/* TC1.CTRLD  bit masks and bit positions */
4924#define TC1_EVACT_gm  0xE0  /* Event Action group mask. */
4925#define TC1_EVACT_gp  5  /* Event Action group position. */
4926#define TC1_EVACT0_bm  (1<<5)  /* Event Action bit 0 mask. */
4927#define TC1_EVACT0_bp  5  /* Event Action bit 0 position. */
4928#define TC1_EVACT1_bm  (1<<6)  /* Event Action bit 1 mask. */
4929#define TC1_EVACT1_bp  6  /* Event Action bit 1 position. */
4930#define TC1_EVACT2_bm  (1<<7)  /* Event Action bit 2 mask. */
4931#define TC1_EVACT2_bp  7  /* Event Action bit 2 position. */
4932
4933#define TC1_EVDLY_bm  0x10  /* Event Delay bit mask. */
4934#define TC1_EVDLY_bp  4  /* Event Delay bit position. */
4935
4936#define TC1_EVSEL_gm  0x0F  /* Event Source Select group mask. */
4937#define TC1_EVSEL_gp  0  /* Event Source Select group position. */
4938#define TC1_EVSEL0_bm  (1<<0)  /* Event Source Select bit 0 mask. */
4939#define TC1_EVSEL0_bp  0  /* Event Source Select bit 0 position. */
4940#define TC1_EVSEL1_bm  (1<<1)  /* Event Source Select bit 1 mask. */
4941#define TC1_EVSEL1_bp  1  /* Event Source Select bit 1 position. */
4942#define TC1_EVSEL2_bm  (1<<2)  /* Event Source Select bit 2 mask. */
4943#define TC1_EVSEL2_bp  2  /* Event Source Select bit 2 position. */
4944#define TC1_EVSEL3_bm  (1<<3)  /* Event Source Select bit 3 mask. */
4945#define TC1_EVSEL3_bp  3  /* Event Source Select bit 3 position. */
4946
4947
4948/* TC1.CTRLE  bit masks and bit positions */
4949#define TC1_DTHM_bm  0x02  /* Dead Time Hold Mode bit mask. */
4950#define TC1_DTHM_bp  1  /* Dead Time Hold Mode bit position. */
4951
4952#define TC1_BYTEM_bm  0x01  /* Byte Mode bit mask. */
4953#define TC1_BYTEM_bp  0  /* Byte Mode bit position. */
4954
4955
4956/* TC1.INTCTRLA  bit masks and bit positions */
4957#define TC1_ERRINTLVL_gm  0x0C  /* Error Interrupt Level group mask. */
4958#define TC1_ERRINTLVL_gp  2  /* Error Interrupt Level group position. */
4959#define TC1_ERRINTLVL0_bm  (1<<2)  /* Error Interrupt Level bit 0 mask. */
4960#define TC1_ERRINTLVL0_bp  2  /* Error Interrupt Level bit 0 position. */
4961#define TC1_ERRINTLVL1_bm  (1<<3)  /* Error Interrupt Level bit 1 mask. */
4962#define TC1_ERRINTLVL1_bp  3  /* Error Interrupt Level bit 1 position. */
4963
4964#define TC1_OVFINTLVL_gm  0x03  /* Overflow interrupt level group mask. */
4965#define TC1_OVFINTLVL_gp  0  /* Overflow interrupt level group position. */
4966#define TC1_OVFINTLVL0_bm  (1<<0)  /* Overflow interrupt level bit 0 mask. */
4967#define TC1_OVFINTLVL0_bp  0  /* Overflow interrupt level bit 0 position. */
4968#define TC1_OVFINTLVL1_bm  (1<<1)  /* Overflow interrupt level bit 1 mask. */
4969#define TC1_OVFINTLVL1_bp  1  /* Overflow interrupt level bit 1 position. */
4970
4971
4972/* TC1.INTCTRLB  bit masks and bit positions */
4973#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
4974#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
4975#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
4976#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
4977#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
4978#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
4979
4980#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
4981#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
4982#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
4983#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
4984#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
4985#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
4986
4987
4988/* TC1.CTRLFCLR  bit masks and bit positions */
4989#define TC1_CMD_gm  0x0C  /* Command group mask. */
4990#define TC1_CMD_gp  2  /* Command group position. */
4991#define TC1_CMD0_bm  (1<<2)  /* Command bit 0 mask. */
4992#define TC1_CMD0_bp  2  /* Command bit 0 position. */
4993#define TC1_CMD1_bm  (1<<3)  /* Command bit 1 mask. */
4994#define TC1_CMD1_bp  3  /* Command bit 1 position. */
4995
4996#define TC1_LUPD_bm  0x02  /* Lock Update bit mask. */
4997#define TC1_LUPD_bp  1  /* Lock Update bit position. */
4998
4999#define TC1_DIR_bm  0x01  /* Direction bit mask. */
5000#define TC1_DIR_bp  0  /* Direction bit position. */
5001
5002
5003/* TC1.CTRLFSET  bit masks and bit positions */
5004/* TC1_CMD_gm  Predefined. */
5005/* TC1_CMD_gp  Predefined. */
5006/* TC1_CMD0_bm  Predefined. */
5007/* TC1_CMD0_bp  Predefined. */
5008/* TC1_CMD1_bm  Predefined. */
5009/* TC1_CMD1_bp  Predefined. */
5010
5011/* TC1_LUPD_bm  Predefined. */
5012/* TC1_LUPD_bp  Predefined. */
5013
5014/* TC1_DIR_bm  Predefined. */
5015/* TC1_DIR_bp  Predefined. */
5016
5017
5018/* TC1.CTRLGCLR  bit masks and bit positions */
5019#define TC1_CCBBV_bm  0x04  /* Compare or Capture B Buffer Valid bit mask. */
5020#define TC1_CCBBV_bp  2  /* Compare or Capture B Buffer Valid bit position. */
5021
5022#define TC1_CCABV_bm  0x02  /* Compare or Capture A Buffer Valid bit mask. */
5023#define TC1_CCABV_bp  1  /* Compare or Capture A Buffer Valid bit position. */
5024
5025#define TC1_PERBV_bm  0x01  /* Period Buffer Valid bit mask. */
5026#define TC1_PERBV_bp  0  /* Period Buffer Valid bit position. */
5027
5028
5029/* TC1.CTRLGSET  bit masks and bit positions */
5030/* TC1_CCBBV_bm  Predefined. */
5031/* TC1_CCBBV_bp  Predefined. */
5032
5033/* TC1_CCABV_bm  Predefined. */
5034/* TC1_CCABV_bp  Predefined. */
5035
5036/* TC1_PERBV_bm  Predefined. */
5037/* TC1_PERBV_bp  Predefined. */
5038
5039
5040/* TC1.INTFLAGS  bit masks and bit positions */
5041#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
5042#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
5043
5044#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
5045#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
5046
5047#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
5048#define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
5049
5050#define TC1_OVFIF_bm  0x01  /* Overflow Interrupt Flag bit mask. */
5051#define TC1_OVFIF_bp  0  /* Overflow Interrupt Flag bit position. */
5052
5053
5054/* AWEX.CTRL  bit masks and bit positions */
5055#define AWEX_PGM_bm  0x20  /* Pattern Generation Mode bit mask. */
5056#define AWEX_PGM_bp  5  /* Pattern Generation Mode bit position. */
5057
5058#define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
5059#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
5060
5061#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
5062#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
5063
5064#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
5065#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
5066
5067#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
5068#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
5069
5070#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
5071#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
5072
5073
5074/* AWEX.FDCTRL  bit masks and bit positions */
5075#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
5076#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
5077
5078#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
5079#define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
5080
5081#define AWEX_FDACT_gm  0x03  /* Fault Detect Action group mask. */
5082#define AWEX_FDACT_gp  0  /* Fault Detect Action group position. */
5083#define AWEX_FDACT0_bm  (1<<0)  /* Fault Detect Action bit 0 mask. */
5084#define AWEX_FDACT0_bp  0  /* Fault Detect Action bit 0 position. */
5085#define AWEX_FDACT1_bm  (1<<1)  /* Fault Detect Action bit 1 mask. */
5086#define AWEX_FDACT1_bp  1  /* Fault Detect Action bit 1 position. */
5087
5088
5089/* AWEX.STATUS  bit masks and bit positions */
5090#define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
5091#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
5092
5093#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
5094#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
5095
5096#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
5097#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
5098
5099
5100/* HIRES.CTRL  bit masks and bit positions */
5101#define HIRES_HREN_gm  0x03  /* High Resolution Enable group mask. */
5102#define HIRES_HREN_gp  0  /* High Resolution Enable group position. */
5103#define HIRES_HREN0_bm  (1<<0)  /* High Resolution Enable bit 0 mask. */
5104#define HIRES_HREN0_bp  0  /* High Resolution Enable bit 0 position. */
5105#define HIRES_HREN1_bm  (1<<1)  /* High Resolution Enable bit 1 mask. */
5106#define HIRES_HREN1_bp  1  /* High Resolution Enable bit 1 position. */
5107
5108
5109/* USART - Universal Asynchronous Receiver-Transmitter */
5110/* USART.STATUS  bit masks and bit positions */
5111#define USART_RXCIF_bm  0x80  /* Receive Interrupt Flag bit mask. */
5112#define USART_RXCIF_bp  7  /* Receive Interrupt Flag bit position. */
5113
5114#define USART_TXCIF_bm  0x40  /* Transmit Interrupt Flag bit mask. */
5115#define USART_TXCIF_bp  6  /* Transmit Interrupt Flag bit position. */
5116
5117#define USART_DREIF_bm  0x20  /* Data Register Empty Flag bit mask. */
5118#define USART_DREIF_bp  5  /* Data Register Empty Flag bit position. */
5119
5120#define USART_FERR_bm  0x10  /* Frame Error bit mask. */
5121#define USART_FERR_bp  4  /* Frame Error bit position. */
5122
5123#define USART_BUFOVF_bm  0x08  /* Buffer Overflow bit mask. */
5124#define USART_BUFOVF_bp  3  /* Buffer Overflow bit position. */
5125
5126#define USART_PERR_bm  0x04  /* Parity Error bit mask. */
5127#define USART_PERR_bp  2  /* Parity Error bit position. */
5128
5129#define USART_RXB8_bm  0x01  /* Receive Bit 8 bit mask. */
5130#define USART_RXB8_bp  0  /* Receive Bit 8 bit position. */
5131
5132
5133/* USART.CTRLA  bit masks and bit positions */
5134#define USART_RXCINTLVL_gm  0x30  /* Receive Interrupt Level group mask. */
5135#define USART_RXCINTLVL_gp  4  /* Receive Interrupt Level group position. */
5136#define USART_RXCINTLVL0_bm  (1<<4)  /* Receive Interrupt Level bit 0 mask. */
5137#define USART_RXCINTLVL0_bp  4  /* Receive Interrupt Level bit 0 position. */
5138#define USART_RXCINTLVL1_bm  (1<<5)  /* Receive Interrupt Level bit 1 mask. */
5139#define USART_RXCINTLVL1_bp  5  /* Receive Interrupt Level bit 1 position. */
5140
5141#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
5142#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
5143#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
5144#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
5145#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
5146#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
5147
5148#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
5149#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
5150#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
5151#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
5152#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
5153#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
5154
5155
5156/* USART.CTRLB  bit masks and bit positions */
5157#define USART_RXEN_bm  0x10  /* Receiver Enable bit mask. */
5158#define USART_RXEN_bp  4  /* Receiver Enable bit position. */
5159
5160#define USART_TXEN_bm  0x08  /* Transmitter Enable bit mask. */
5161#define USART_TXEN_bp  3  /* Transmitter Enable bit position. */
5162
5163#define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
5164#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
5165
5166#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
5167#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
5168
5169#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
5170#define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
5171
5172
5173/* USART.CTRLC  bit masks and bit positions */
5174#define USART_CMODE_gm  0xC0  /* Communication Mode group mask. */
5175#define USART_CMODE_gp  6  /* Communication Mode group position. */
5176#define USART_CMODE0_bm  (1<<6)  /* Communication Mode bit 0 mask. */
5177#define USART_CMODE0_bp  6  /* Communication Mode bit 0 position. */
5178#define USART_CMODE1_bm  (1<<7)  /* Communication Mode bit 1 mask. */
5179#define USART_CMODE1_bp  7  /* Communication Mode bit 1 position. */
5180
5181#define USART_PMODE_gm  0x30  /* Parity Mode group mask. */
5182#define USART_PMODE_gp  4  /* Parity Mode group position. */
5183#define USART_PMODE0_bm  (1<<4)  /* Parity Mode bit 0 mask. */
5184#define USART_PMODE0_bp  4  /* Parity Mode bit 0 position. */
5185#define USART_PMODE1_bm  (1<<5)  /* Parity Mode bit 1 mask. */
5186#define USART_PMODE1_bp  5  /* Parity Mode bit 1 position. */
5187
5188#define USART_SBMODE_bm  0x08  /* Stop Bit Mode bit mask. */
5189#define USART_SBMODE_bp  3  /* Stop Bit Mode bit position. */
5190
5191#define USART_CHSIZE_gm  0x07  /* Character Size group mask. */
5192#define USART_CHSIZE_gp  0  /* Character Size group position. */
5193#define USART_CHSIZE0_bm  (1<<0)  /* Character Size bit 0 mask. */
5194#define USART_CHSIZE0_bp  0  /* Character Size bit 0 position. */
5195#define USART_CHSIZE1_bm  (1<<1)  /* Character Size bit 1 mask. */
5196#define USART_CHSIZE1_bp  1  /* Character Size bit 1 position. */
5197#define USART_CHSIZE2_bm  (1<<2)  /* Character Size bit 2 mask. */
5198#define USART_CHSIZE2_bp  2  /* Character Size bit 2 position. */
5199
5200
5201/* USART.BAUDCTRLA  bit masks and bit positions */
5202#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
5203#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
5204#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
5205#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
5206#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
5207#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
5208#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
5209#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
5210#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
5211#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
5212#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
5213#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
5214#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
5215#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
5216#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
5217#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
5218#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
5219#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
5220
5221
5222/* USART.BAUDCTRLB  bit masks and bit positions */
5223#define USART_BSCALE_gm  0xF0  /* Baud Rate Scale group mask. */
5224#define USART_BSCALE_gp  4  /* Baud Rate Scale group position. */
5225#define USART_BSCALE0_bm  (1<<4)  /* Baud Rate Scale bit 0 mask. */
5226#define USART_BSCALE0_bp  4  /* Baud Rate Scale bit 0 position. */
5227#define USART_BSCALE1_bm  (1<<5)  /* Baud Rate Scale bit 1 mask. */
5228#define USART_BSCALE1_bp  5  /* Baud Rate Scale bit 1 position. */
5229#define USART_BSCALE2_bm  (1<<6)  /* Baud Rate Scale bit 2 mask. */
5230#define USART_BSCALE2_bp  6  /* Baud Rate Scale bit 2 position. */
5231#define USART_BSCALE3_bm  (1<<7)  /* Baud Rate Scale bit 3 mask. */
5232#define USART_BSCALE3_bp  7  /* Baud Rate Scale bit 3 position. */
5233
5234/* USART_BSEL_gm  Predefined. */
5235/* USART_BSEL_gp  Predefined. */
5236/* USART_BSEL0_bm  Predefined. */
5237/* USART_BSEL0_bp  Predefined. */
5238/* USART_BSEL1_bm  Predefined. */
5239/* USART_BSEL1_bp  Predefined. */
5240/* USART_BSEL2_bm  Predefined. */
5241/* USART_BSEL2_bp  Predefined. */
5242/* USART_BSEL3_bm  Predefined. */
5243/* USART_BSEL3_bp  Predefined. */
5244
5245
5246/* SPI - Serial Peripheral Interface */
5247/* SPI.CTRL  bit masks and bit positions */
5248#define SPI_CLK2X_bm  0x80  /* Enable Double Speed bit mask. */
5249#define SPI_CLK2X_bp  7  /* Enable Double Speed bit position. */
5250
5251#define SPI_ENABLE_bm  0x40  /* Enable Module bit mask. */
5252#define SPI_ENABLE_bp  6  /* Enable Module bit position. */
5253
5254#define SPI_DORD_bm  0x20  /* Data Order Setting bit mask. */
5255#define SPI_DORD_bp  5  /* Data Order Setting bit position. */
5256
5257#define SPI_MASTER_bm  0x10  /* Master Operation Enable bit mask. */
5258#define SPI_MASTER_bp  4  /* Master Operation Enable bit position. */
5259
5260#define SPI_MODE_gm  0x0C  /* SPI Mode group mask. */
5261#define SPI_MODE_gp  2  /* SPI Mode group position. */
5262#define SPI_MODE0_bm  (1<<2)  /* SPI Mode bit 0 mask. */
5263#define SPI_MODE0_bp  2  /* SPI Mode bit 0 position. */
5264#define SPI_MODE1_bm  (1<<3)  /* SPI Mode bit 1 mask. */
5265#define SPI_MODE1_bp  3  /* SPI Mode bit 1 position. */
5266
5267#define SPI_PRESCALER_gm  0x03  /* Prescaler group mask. */
5268#define SPI_PRESCALER_gp  0  /* Prescaler group position. */
5269#define SPI_PRESCALER0_bm  (1<<0)  /* Prescaler bit 0 mask. */
5270#define SPI_PRESCALER0_bp  0  /* Prescaler bit 0 position. */
5271#define SPI_PRESCALER1_bm  (1<<1)  /* Prescaler bit 1 mask. */
5272#define SPI_PRESCALER1_bp  1  /* Prescaler bit 1 position. */
5273
5274
5275/* SPI.INTCTRL  bit masks and bit positions */
5276#define SPI_INTLVL_gm  0x03  /* Interrupt level group mask. */
5277#define SPI_INTLVL_gp  0  /* Interrupt level group position. */
5278#define SPI_INTLVL0_bm  (1<<0)  /* Interrupt level bit 0 mask. */
5279#define SPI_INTLVL0_bp  0  /* Interrupt level bit 0 position. */
5280#define SPI_INTLVL1_bm  (1<<1)  /* Interrupt level bit 1 mask. */
5281#define SPI_INTLVL1_bp  1  /* Interrupt level bit 1 position. */
5282
5283
5284/* SPI.STATUS  bit masks and bit positions */
5285#define SPI_IF_bm  0x80  /* Interrupt Flag bit mask. */
5286#define SPI_IF_bp  7  /* Interrupt Flag bit position. */
5287
5288#define SPI_WRCOL_bm  0x40  /* Write Collision bit mask. */
5289#define SPI_WRCOL_bp  6  /* Write Collision bit position. */
5290
5291
5292/* IRCOM - IR Communication Module */
5293/* IRCOM.CTRL  bit masks and bit positions */
5294#define IRCOM_EVSEL_gm  0x0F  /* Event Channel Select group mask. */
5295#define IRCOM_EVSEL_gp  0  /* Event Channel Select group position. */
5296#define IRCOM_EVSEL0_bm  (1<<0)  /* Event Channel Select bit 0 mask. */
5297#define IRCOM_EVSEL0_bp  0  /* Event Channel Select bit 0 position. */
5298#define IRCOM_EVSEL1_bm  (1<<1)  /* Event Channel Select bit 1 mask. */
5299#define IRCOM_EVSEL1_bp  1  /* Event Channel Select bit 1 position. */
5300#define IRCOM_EVSEL2_bm  (1<<2)  /* Event Channel Select bit 2 mask. */
5301#define IRCOM_EVSEL2_bp  2  /* Event Channel Select bit 2 position. */
5302#define IRCOM_EVSEL3_bm  (1<<3)  /* Event Channel Select bit 3 mask. */
5303#define IRCOM_EVSEL3_bp  3  /* Event Channel Select bit 3 position. */
5304
5305
5306
5307// Generic Port Pins
5308
5309#define PIN0_bm 0x01
5310#define PIN0_bp 0
5311#define PIN1_bm 0x02
5312#define PIN1_bp 1
5313#define PIN2_bm 0x04
5314#define PIN2_bp 2
5315#define PIN3_bm 0x08
5316#define PIN3_bp 3
5317#define PIN4_bm 0x10
5318#define PIN4_bp 4
5319#define PIN5_bm 0x20
5320#define PIN5_bp 5
5321#define PIN6_bm 0x40
5322#define PIN6_bp 6
5323#define PIN7_bm 0x80
5324#define PIN7_bp 7
5325
5326
5327/* ========== Interrupt Vector Definitions ========== */
5328/* Vector 0 is the reset vector */
5329
5330/* OSC interrupt vectors */
5331#define OSC_XOSCF_vect_num  1
5332#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
5333
5334/* PORTC interrupt vectors */
5335#define PORTC_INT0_vect_num  2
5336#define PORTC_INT0_vect      _VECTOR(2)  /* External Interrupt 0 */
5337#define PORTC_INT1_vect_num  3
5338#define PORTC_INT1_vect      _VECTOR(3)  /* External Interrupt 1 */
5339
5340/* PORTR interrupt vectors */
5341#define PORTR_INT0_vect_num  4
5342#define PORTR_INT0_vect      _VECTOR(4)  /* External Interrupt 0 */
5343#define PORTR_INT1_vect_num  5
5344#define PORTR_INT1_vect      _VECTOR(5)  /* External Interrupt 1 */
5345
5346/* RTC interrupt vectors */
5347#define RTC_OVF_vect_num  10
5348#define RTC_OVF_vect      _VECTOR(10)  /* Overflow Interrupt */
5349#define RTC_COMP_vect_num  11
5350#define RTC_COMP_vect      _VECTOR(11)  /* Compare Interrupt */
5351
5352/* TWIC interrupt vectors */
5353#define TWIC_TWIS_vect_num  12
5354#define TWIC_TWIS_vect      _VECTOR(12)  /* TWI Slave Interrupt */
5355#define TWIC_TWIM_vect_num  13
5356#define TWIC_TWIM_vect      _VECTOR(13)  /* TWI Master Interrupt */
5357
5358/* TCC0 interrupt vectors */
5359#define TCC0_OVF_vect_num  14
5360#define TCC0_OVF_vect      _VECTOR(14)  /* Overflow Interrupt */
5361#define TCC0_ERR_vect_num  15
5362#define TCC0_ERR_vect      _VECTOR(15)  /* Error Interrupt */
5363#define TCC0_CCA_vect_num  16
5364#define TCC0_CCA_vect      _VECTOR(16)  /* Compare or Capture A Interrupt */
5365#define TCC0_CCB_vect_num  17
5366#define TCC0_CCB_vect      _VECTOR(17)  /* Compare or Capture B Interrupt */
5367#define TCC0_CCC_vect_num  18
5368#define TCC0_CCC_vect      _VECTOR(18)  /* Compare or Capture C Interrupt */
5369#define TCC0_CCD_vect_num  19
5370#define TCC0_CCD_vect      _VECTOR(19)  /* Compare or Capture D Interrupt */
5371
5372/* TCC1 interrupt vectors */
5373#define TCC1_OVF_vect_num  20
5374#define TCC1_OVF_vect      _VECTOR(20)  /* Overflow Interrupt */
5375#define TCC1_ERR_vect_num  21
5376#define TCC1_ERR_vect      _VECTOR(21)  /* Error Interrupt */
5377#define TCC1_CCA_vect_num  22
5378#define TCC1_CCA_vect      _VECTOR(22)  /* Compare or Capture A Interrupt */
5379#define TCC1_CCB_vect_num  23
5380#define TCC1_CCB_vect      _VECTOR(23)  /* Compare or Capture B Interrupt */
5381
5382/* SPIC interrupt vectors */
5383#define SPIC_INT_vect_num  24
5384#define SPIC_INT_vect      _VECTOR(24)  /* SPI Interrupt */
5385
5386/* USARTC0 interrupt vectors */
5387#define USARTC0_RXC_vect_num  25
5388#define USARTC0_RXC_vect      _VECTOR(25)  /* Reception Complete Interrupt */
5389#define USARTC0_DRE_vect_num  26
5390#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
5391#define USARTC0_TXC_vect_num  27
5392#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
5393
5394/* NVM interrupt vectors */
5395#define NVM_EE_vect_num  32
5396#define NVM_EE_vect      _VECTOR(32)  /* EE Interrupt */
5397#define NVM_SPM_vect_num  33
5398#define NVM_SPM_vect      _VECTOR(33)  /* SPM Interrupt */
5399
5400/* PORTB interrupt vectors */
5401#define PORTB_INT0_vect_num  34
5402#define PORTB_INT0_vect      _VECTOR(34)  /* External Interrupt 0 */
5403#define PORTB_INT1_vect_num  35
5404#define PORTB_INT1_vect      _VECTOR(35)  /* External Interrupt 1 */
5405
5406/* PORTE interrupt vectors */
5407#define PORTE_INT0_vect_num  43
5408#define PORTE_INT0_vect      _VECTOR(43)  /* External Interrupt 0 */
5409#define PORTE_INT1_vect_num  44
5410#define PORTE_INT1_vect      _VECTOR(44)  /* External Interrupt 1 */
5411
5412/* TWIE interrupt vectors */
5413#define TWIE_TWIS_vect_num  45
5414#define TWIE_TWIS_vect      _VECTOR(45)  /* TWI Slave Interrupt */
5415#define TWIE_TWIM_vect_num  46
5416#define TWIE_TWIM_vect      _VECTOR(46)  /* TWI Master Interrupt */
5417
5418/* TCE0 interrupt vectors */
5419#define TCE0_OVF_vect_num  47
5420#define TCE0_OVF_vect      _VECTOR(47)  /* Overflow Interrupt */
5421#define TCE0_ERR_vect_num  48
5422#define TCE0_ERR_vect      _VECTOR(48)  /* Error Interrupt */
5423#define TCE0_CCA_vect_num  49
5424#define TCE0_CCA_vect      _VECTOR(49)  /* Compare or Capture A Interrupt */
5425#define TCE0_CCB_vect_num  50
5426#define TCE0_CCB_vect      _VECTOR(50)  /* Compare or Capture B Interrupt */
5427#define TCE0_CCC_vect_num  51
5428#define TCE0_CCC_vect      _VECTOR(51)  /* Compare or Capture C Interrupt */
5429#define TCE0_CCD_vect_num  52
5430#define TCE0_CCD_vect      _VECTOR(52)  /* Compare or Capture D Interrupt */
5431
5432/* PORTD interrupt vectors */
5433#define PORTD_INT0_vect_num  64
5434#define PORTD_INT0_vect      _VECTOR(64)  /* External Interrupt 0 */
5435#define PORTD_INT1_vect_num  65
5436#define PORTD_INT1_vect      _VECTOR(65)  /* External Interrupt 1 */
5437
5438/* PORTA interrupt vectors */
5439#define PORTA_INT0_vect_num  66
5440#define PORTA_INT0_vect      _VECTOR(66)  /* External Interrupt 0 */
5441#define PORTA_INT1_vect_num  67
5442#define PORTA_INT1_vect      _VECTOR(67)  /* External Interrupt 1 */
5443
5444/* ACA interrupt vectors */
5445#define ACA_AC0_vect_num  68
5446#define ACA_AC0_vect      _VECTOR(68)  /* AC0 Interrupt */
5447#define ACA_AC1_vect_num  69
5448#define ACA_AC1_vect      _VECTOR(69)  /* AC1 Interrupt */
5449#define ACA_ACW_vect_num  70
5450#define ACA_ACW_vect      _VECTOR(70)  /* ACW Window Mode Interrupt */
5451
5452/* ADCA interrupt vectors */
5453#define ADCA_CH0_vect_num  71
5454#define ADCA_CH0_vect      _VECTOR(71)  /* Interrupt 0 */
5455
5456/* TCD0 interrupt vectors */
5457#define TCD0_OVF_vect_num  77
5458#define TCD0_OVF_vect      _VECTOR(77)  /* Overflow Interrupt */
5459#define TCD0_ERR_vect_num  78
5460#define TCD0_ERR_vect      _VECTOR(78)  /* Error Interrupt */
5461#define TCD0_CCA_vect_num  79
5462#define TCD0_CCA_vect      _VECTOR(79)  /* Compare or Capture A Interrupt */
5463#define TCD0_CCB_vect_num  80
5464#define TCD0_CCB_vect      _VECTOR(80)  /* Compare or Capture B Interrupt */
5465#define TCD0_CCC_vect_num  81
5466#define TCD0_CCC_vect      _VECTOR(81)  /* Compare or Capture C Interrupt */
5467#define TCD0_CCD_vect_num  82
5468#define TCD0_CCD_vect      _VECTOR(82)  /* Compare or Capture D Interrupt */
5469
5470/* SPID interrupt vectors */
5471#define SPID_INT_vect_num  87
5472#define SPID_INT_vect      _VECTOR(87)  /* SPI Interrupt */
5473
5474/* USARTD0 interrupt vectors */
5475#define USARTD0_RXC_vect_num  88
5476#define USARTD0_RXC_vect      _VECTOR(88)  /* Reception Complete Interrupt */
5477#define USARTD0_DRE_vect_num  89
5478#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
5479#define USARTD0_TXC_vect_num  90
5480#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
5481
5482
5483#define _VECTOR_SIZE 4 /* Size of individual vector. */
5484#define _VECTORS_SIZE (91 * _VECTOR_SIZE)
5485
5486
5487/* ========== Constants ========== */
5488
5489#define PROGMEM_START     (0x0000)
5490#define PROGMEM_SIZE      (36864)
5491#define PROGMEM_PAGE_SIZE (256)
5492#define PROGMEM_END       (PROGMEM_START + PROGMEM_SIZE - 1)
5493
5494#define APP_SECTION_START     (0x0000)
5495#define APP_SECTION_SIZE      (32768)
5496#define APP_SECTION_PAGE_SIZE (256)
5497#define APP_SECTION_END       (APP_SECTION_START + APP_SECTION_SIZE - 1)
5498
5499#define APPTABLE_SECTION_START     (0x7000)
5500#define APPTABLE_SECTION_SIZE      (4096)
5501#define APPTABLE_SECTION_PAGE_SIZE (256)
5502#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
5503
5504#define BOOT_SECTION_START     (0x8000)
5505#define BOOT_SECTION_SIZE      (4096)
5506#define BOOT_SECTION_PAGE_SIZE (256)
5507#define BOOT_SECTION_END       (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
5508
5509#define DATAMEM_START     (0x0000)
5510#define DATAMEM_SIZE      (12288)
5511#define DATAMEM_PAGE_SIZE (0)
5512#define DATAMEM_END       (DATAMEM_START + DATAMEM_SIZE - 1)
5513
5514#define IO_START     (0x0000)
5515#define IO_SIZE      (4096)
5516#define IO_PAGE_SIZE (0)
5517#define IO_END       (IO_START + IO_SIZE - 1)
5518
5519#define MAPPED_EEPROM_START     (0x1000)
5520#define MAPPED_EEPROM_SIZE      (1024)
5521#define MAPPED_EEPROM_PAGE_SIZE (0)
5522#define MAPPED_EEPROM_END       (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
5523
5524#define INTERNAL_SRAM_START     (0x2000)
5525#define INTERNAL_SRAM_SIZE      (4096)
5526#define INTERNAL_SRAM_PAGE_SIZE (0)
5527#define INTERNAL_SRAM_END       (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
5528
5529#define EEPROM_START     (0x0000)
5530#define EEPROM_SIZE      (1024)
5531#define EEPROM_PAGE_SIZE (32)
5532#define EEPROM_END       (EEPROM_START + EEPROM_SIZE - 1)
5533
5534#define FUSE_START     (0x0000)
5535#define FUSE_SIZE      (6)
5536#define FUSE_PAGE_SIZE (0)
5537#define FUSE_END       (FUSE_START + FUSE_SIZE - 1)
5538
5539#define LOCKBIT_START     (0x0000)
5540#define LOCKBIT_SIZE      (1)
5541#define LOCKBIT_PAGE_SIZE (0)
5542#define LOCKBIT_END       (LOCKBIT_START + LOCKBIT_SIZE - 1)
5543
5544#define SIGNATURES_START     (0x0000)
5545#define SIGNATURES_SIZE      (3)
5546#define SIGNATURES_PAGE_SIZE (0)
5547#define SIGNATURES_END       (SIGNATURES_START + SIGNATURES_SIZE - 1)
5548
5549#define USER_SIGNATURES_START     (0x0000)
5550#define USER_SIGNATURES_SIZE      (256)
5551#define USER_SIGNATURES_PAGE_SIZE (0)
5552#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
5553
5554#define PROD_SIGNATURES_START     (0x0000)
5555#define PROD_SIGNATURES_SIZE      (52)
5556#define PROD_SIGNATURES_PAGE_SIZE (0)
5557#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
5558
5559#define FLASHEND     PROGMEM_END
5560#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
5561#define RAMSTART     INTERNAL_SRAM_START
5562#define RAMSIZE      INTERNAL_SRAM_SIZE
5563#define RAMEND       INTERNAL_SRAM_END
5564#define XRAMSTART    EXTERNAL_SRAM_START
5565#define XRAMSIZE     EXTERNAL_SRAM_SIZE
5566#define XRAMEND      INTERNAL_SRAM_END
5567#define E2END        EEPROM_END
5568#define E2PAGESIZE   EEPROM_PAGE_SIZE
5569
5570
5571/* ========== Fuses ========== */
5572#define FUSE_MEMORY_SIZE 6
5573
5574/* Fuse Byte 0 */
5575#define FUSE_USERID0  (unsigned char)~_BV(0)  /* User ID Bit 0 */
5576#define FUSE_USERID1  (unsigned char)~_BV(1)  /* User ID Bit 1 */
5577#define FUSE_USERID2  (unsigned char)~_BV(2)  /* User ID Bit 2 */
5578#define FUSE_USERID3  (unsigned char)~_BV(3)  /* User ID Bit 3 */
5579#define FUSE_USERID4  (unsigned char)~_BV(4)  /* User ID Bit 4 */
5580#define FUSE_USERID5  (unsigned char)~_BV(5)  /* User ID Bit 5 */
5581#define FUSE_USERID6  (unsigned char)~_BV(6)  /* User ID Bit 6 */
5582#define FUSE_USERID7  (unsigned char)~_BV(7)  /* User ID Bit 7 */
5583#define FUSE0_DEFAULT  (0xFF)
5584
5585/* Fuse Byte 1 */
5586#define FUSE_WDP0  (unsigned char)~_BV(0)  /* Watchdog Timeout Period Bit 0 */
5587#define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
5588#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
5589#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
5590#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
5591#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
5592#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
5593#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
5594#define FUSE1_DEFAULT  (0xFF)
5595
5596/* Fuse Byte 2 */
5597#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
5598#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
5599#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
5600#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
5601#define FUSE2_DEFAULT  (0xFF)
5602
5603/* Fuse Byte 3 Reserved */
5604
5605/* Fuse Byte 4 */
5606#define FUSE_WDLOCK  (unsigned char)~_BV(1)  /* Watchdog Timer Lock */
5607#define FUSE_SUT0  (unsigned char)~_BV(2)  /* Start-up Time Bit 0 */
5608#define FUSE_SUT1  (unsigned char)~_BV(3)  /* Start-up Time Bit 1 */
5609#define FUSE4_DEFAULT  (0xFF)
5610
5611/* Fuse Byte 5 */
5612#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
5613#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
5614#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
5615#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
5616#define FUSE_BODACT0  (unsigned char)~_BV(4)  /* BOD Operation in Active Mode Bit 0 */
5617#define FUSE_BODACT1  (unsigned char)~_BV(5)  /* BOD Operation in Active Mode Bit 1 */
5618#define FUSE5_DEFAULT  (0xFF)
5619
5620
5621/* ========== Lock Bits ========== */
5622#define __LOCK_BITS_EXIST
5623#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
5624#define __BOOT_LOCK_APPLICATION_BITS_EXIST
5625#define __BOOT_LOCK_BOOT_BITS_EXIST
5626
5627
5628/* ========== Signature ========== */
5629#define SIGNATURE_0 0x1E
5630#define SIGNATURE_1 0x95
5631#define SIGNATURE_2 0x42
5632
5633
5634#endif /* _AVR_ATxmega32D4_H_ */
5635
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