source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/hardware/tools/avr/lib/gcc/avr/4.9.2/plugin/include/rtl.def @ 4837

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1/* This file contains the definitions and documentation for the
2   Register Transfer Expressions (rtx's) that make up the
3   Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4   Copyright (C) 1987-2014 Free Software Foundation, Inc.
6This file is part of GCC.
8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 3, or (at your option) any later
13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16for more details.
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING3.  If not see
20<>.  */
23/* Expression definitions and descriptions for all targets are in this file.
24   Some will not be used for some targets.
26   The fields in the cpp macro call "DEF_RTL_EXPR()"
27   are used to create declarations in the C source of the compiler.
29   The fields are:
31   1.  The internal name of the rtx used in the C source.
32   It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
33   By convention these are in UPPER_CASE.
35   2.  The name of the rtx in the external ASCII format read by
36   read_rtx(), and printed by print_rtx().
37   These names are stored in rtx_name[].
38   By convention these are the internal (field 1) names in lower_case.
40   3.  The print format, and type of each rtx->u.fld[] (field) in this rtx.
41   These formats are stored in rtx_format[].
42   The meaning of the formats is documented in front of this array in rtl.c
44   4.  The class of the rtx.  These are stored in rtx_class and are accessed
45   via the GET_RTX_CLASS macro.  They are defined as follows:
48         an rtx code that can be used to represent a constant object
49         (e.g, CONST_INT)
50     RTX_OBJ
51         an rtx code that can be used to represent an object (e.g, REG, MEM)
53         an rtx code for a comparison (e.g, LT, GT)
55         an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
56     RTX_UNARY
57         an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
59         an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
61         an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
63         an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
65         an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
66     RTX_INSN
67         an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) or
68         data that will be output as assembly pseudo-ops (DEBUG_INSN)
69     RTX_MATCH
70         an rtx code for something that matches in insns (e.g, MATCH_DUP)
72         an rtx code for autoincrement addressing modes (e.g. POST_DEC)
73     RTX_EXTRA
74         everything else
76   All of the expressions that appear only in machine descriptions,
77   not in RTL used by the compiler itself, are at the end of the file.  */
79/* Unknown, or no such operation; the enumeration constant should have
80   value zero.  */
83/* Used in the cselib routines to describe a value.  Objects of this
84   kind are only allocated in cselib.c, in an alloc pool instead of in
85   GC memory.  The only operand of a VALUE is a cselib_val.
86   var-tracking requires this to have a distinct integral value from
87   DECL codes in trees.  */
88DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
90/* The RTL generated for a DEBUG_EXPR_DECL.  It links back to the
91   DEBUG_EXPR_DECL in the first operand.  */
92DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ)
94/* ---------------------------------------------------------------------
95   Expressions used in constructing lists.
96   --------------------------------------------------------------------- */
98/* A linked list of expressions.  */
99DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
101/* A linked list of instructions.
102   The insns are represented in print by their uids.  */
103DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
105/* A linked list of integers.  */
106DEF_RTL_EXPR(INT_LIST, "int_list", "ie", RTX_EXTRA)
108/* SEQUENCE is used in late passes of the compiler to group insns for
109   one reason or another.
111   For example, after delay slot filling, branch instructions with filled
112   delay slots are represented as a SEQUENCE of length 1 + n_delay_slots,
113   with the branch instruction in XEXPVEC(seq, 0, 0) and the instructions
114   occupying the delay slots in the remaining XEXPVEC slots.
116   Another place where a SEQUENCE may appear, is in REG_FRAME_RELATED_EXPR
117   notes, to express complex operations that are not obvious from the insn
118   to which the REG_FRAME_RELATED_EXPR note is attached.  In this usage of
119   SEQUENCE, the sequence vector slots do not hold real instructions but
120   only pseudo-instructions that can be translated to DWARF CFA expressions.
122   Some back ends also use SEQUENCE to group insns in bundles.
124   Much of the compiler infrastructure is not prepared to handle SEQUENCE
125   objects.  Only passes after pass_free_cfg are expected to handle them.  */
128/* Represents a non-global base address.  This is only used in alias.c.  */
129DEF_RTL_EXPR(ADDRESS, "address", "i", RTX_EXTRA)
131/* ----------------------------------------------------------------------
132   Expression types used for things in the instruction chain.
134   All formats must start with "iuu" to handle the chain.
135   Each insn expression holds an rtl instruction and its semantics
136   during back-end processing.
137   See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
139   ---------------------------------------------------------------------- */
141/* An annotation for variable assignment tracking.  */
142DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "iuuBeiie", RTX_INSN)
144/* An instruction that cannot jump.  */
145DEF_RTL_EXPR(INSN, "insn", "iuuBeiie", RTX_INSN)
147/* An instruction that can possibly jump.
148   Fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
149DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBeiie0", RTX_INSN)
151/* An instruction that can possibly call a subroutine
152   but which will not change which instruction comes next
153   in the current function.
154   Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
155   All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
156DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBeiiee", RTX_INSN)
158/* Placeholder for tablejump JUMP_INSNs.  The pattern of this kind
159   of rtx is always either an ADDR_VEC or an ADDR_DIFF_VEC.  These
160   placeholders do not appear as real instructions inside a basic
161   block, but are considered active_insn_p instructions for historical
162   reasons, when jump table data was represented with JUMP_INSNs.  */
163DEF_RTL_EXPR(JUMP_TABLE_DATA, "jump_table_data", "iuuBe0000", RTX_INSN)
165/* A marker that indicates that control will not flow through.  */
166DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA)
168/* Holds a label that is followed by instructions.
169   Operand:
170   4: is used in jump.c for the use-count of the label.
171   5: is used in the sh backend.
172   6: is a number that is unique in the entire compilation.
173   7: is the user-given name of the label, if any.  */
174DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
176/* Say where in the code a source line starts, for symbol table's sake.
177   Operand:
178   4: note-specific data
179   5: enum insn_note
180   6: unique number if insn_note == note_insn_deleted_label.  */
181DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
183/* ----------------------------------------------------------------------
184   Top level constituents of INSN, JUMP_INSN and CALL_INSN.
185   ---------------------------------------------------------------------- */
187/* Conditionally execute code.
188   Operand 0 is the condition that if true, the code is executed.
189   Operand 1 is the code to be executed (typically a SET).
191   Semantics are that there are no side effects if the condition
192   is false.  This pattern is created automatically by the if_convert
193   pass run after reload or by target-specific splitters.  */
194DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
196/* Several operations to be done in parallel (perhaps under COND_EXEC).  */
199/* A string that is passed through to the assembler as input.
200     One can obviously pass comments through by using the
201     assembler comment syntax.
202     These occur in an insn all by themselves as the PATTERN.
203     They also appear inside an ASM_OPERANDS
204     as a convenient way to hold a string.  */
205DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
207/* An assembler instruction with operands.
208   1st operand is the instruction template.
209   2nd operand is the constraint for the output.
210   3rd operand is the number of the output this expression refers to.
211     When an insn stores more than one value, a separate ASM_OPERANDS
212     is made for each output; this integer distinguishes them.
213   4th is a vector of values of input operands.
214   5th is a vector of modes and constraints for the input operands.
215     Each element is an ASM_INPUT containing a constraint string
216     and whose mode indicates the mode of the input operand.
217   6th is a vector of labels that may be branched to by the asm.
218   7th is the source line number.  */
219DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA)
221/* A machine-specific operation.
222   1st operand is a vector of operands being used by the operation so that
223     any needed reloads can be done.
224   2nd operand is a unique value saying which of a number of machine-specific
225     operations is to be performed.
226   (Note that the vector must be the first operand because of the way that
227   genrecog.c record positions within an insn.)
229   UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
230   or inside an expression.
231   UNSPEC by itself or as a component of a PARALLEL
232   is currently considered not deletable.
234   FIXME: Replace all uses of UNSPEC that appears by itself or as a component
235   of a PARALLEL with USE.
236   */
237DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
239/* Similar, but a volatile operation and one which may trap.  */
240DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
242/* ----------------------------------------------------------------------
243   Table jump addresses.
244   ---------------------------------------------------------------------- */
246/* Vector of addresses, stored as full words.
247   Each element is a LABEL_REF to a CODE_LABEL whose address we want.  */
248DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
250/* Vector of address differences X0 - BASE, X1 - BASE, ...
251   First operand is BASE; the vector contains the X's.
252   The machine mode of this rtx says how much space to leave
253   for each difference and is adjusted by branch shortening if
254   CASE_VECTOR_SHORTEN_MODE is defined.
255   The third and fourth operands store the target labels with the
256   minimum and maximum addresses respectively.
257   The fifth operand stores flags for use by branch shortening.
258  Set at the start of shorten_branches:
259   min_align: the minimum alignment for any of the target labels.
260   base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
261   min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
262   max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
263   min_after_base: true iff minimum address target label is after BASE.
264   max_after_base: true iff maximum address target label is after BASE.
265  Set by the actual branch shortening process:
266   offset_unsigned: true iff offsets have to be treated as unsigned.
267   scale: scaling that is necessary to make offsets fit into the mode.
269   The third, fourth and fifth operands are only valid when
270   CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
271   compilation.  */
272DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
274/* Memory prefetch, with attributes supported on some targets.
275   Operand 1 is the address of the memory to fetch.
276   Operand 2 is 1 for a write access, 0 otherwise.
277   Operand 3 is the level of temporal locality; 0 means there is no
278   temporal locality and 1, 2, and 3 are for increasing levels of temporal
279   locality.
281   The attributes specified by operands 2 and 3 are ignored for targets
282   whose prefetch instructions do not support them.  */
283DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
285/* ----------------------------------------------------------------------
286   At the top level of an instruction (perhaps under PARALLEL).
287   ---------------------------------------------------------------------- */
289/* Assignment.
290   Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
291   Operand 2 is the value stored there.
292   ALL assignment must use SET.
293   Instructions that do multiple assignments must use multiple SET,
294   under PARALLEL.  */
295DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
297/* Indicate something is used in a way that we don't want to explain.
298   For example, subroutine calls will use the register
299   in which the static chain is passed.
301   USE can not appear as an operand of other rtx except for PARALLEL.
302   USE is not deletable, as it indicates that the operand
303   is used in some unknown way.  */
304DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
306/* Indicate something is clobbered in a way that we don't want to explain.
307   For example, subroutine calls will clobber some physical registers
308   (the ones that are by convention not saved).
310   CLOBBER can not appear as an operand of other rtx except for PARALLEL.
311   CLOBBER of a hard register appearing by itself (not within PARALLEL)
312   is considered undeletable before reload.  */
313DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
315/* Call a subroutine.
316   Operand 1 is the address to call.
317   Operand 2 is the number of arguments.  */
319DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
321/* Return from a subroutine.  */
323DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
325/* Like RETURN, but truly represents only a function return, while
326   RETURN may represent an insn that also performs other functions
327   of the function epilogue.  Like RETURN, this may also occur in
328   conditional jumps.  */
329DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA)
331/* Special for EH return from subroutine.  */
333DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
335/* Conditional trap.
336   Operand 1 is the condition.
337   Operand 2 is the trap code.
338   For an unconditional trap, make the condition (const_int 1).  */
339DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
341/* ----------------------------------------------------------------------
342   Primitive values for use in expressions.
343   ---------------------------------------------------------------------- */
345/* numeric integer constant */
346DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
348/* fixed-point constant */
349DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
351/* numeric floating point or integer constant.  If the mode is
352   VOIDmode it is an int otherwise it has a floating point mode and a
353   floating point value.  Operands hold the value.  They are all 'w'
354   and there may be from 2 to 6; see real.h.  */
357/* Describes a vector constant.  */
360/* String constant.  Used for attributes in machine descriptions and
361   for special cases in DWARF2 debug output.  NOT used for source-
362   language string constants.  */
363DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
365/* This is used to encapsulate an expression whose value is constant
366   (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
367   recognized as a constant operand rather than by arithmetic instructions.  */
371/* program counter.  Ordinary jumps are represented
372   by a SET whose first operand is (PC).  */
373DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
375/* A register.  The "operand" is the register number, accessed with
376   the REGNO macro.  If this number is less than FIRST_PSEUDO_REGISTER
377   than a hardware register is being referred to.  The second operand
378   holds the original register number - this will be different for a
379   pseudo register that got turned into a hard register.  The third
380   operand points to a reg_attrs structure.
381   This rtx needs to have as many (or more) fields as a MEM, since we
382   can change REG rtx's into MEMs during reload.  */
383DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
385/* A scratch register.  This represents a register used only within a
386   single insn.  It will be turned into a REG during register allocation
387   or reload unless the constraint indicates that the register won't be
388   needed, in which case it can remain a SCRATCH.  This code is
389   marked as having one operand so it can be turned into a REG.  */
390DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
392/* A reference to a part of another value.  The first operand is the
393   complete value and the second is the byte offset of the selected part.   */
394DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
396/* This one-argument rtx is used for move instructions
397   that are guaranteed to alter only the low part of a destination.
398   Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
399   has an unspecified effect on the high part of REG,
400   but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
401   is guaranteed to alter only the bits of REG that are in HImode.
403   The actual instruction used is probably the same in both cases,
404   but the register constraints may be tighter when STRICT_LOW_PART
405   is in use.  */
407DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
409/* (CONCAT a b) represents the virtual concatenation of a and b
410   to make a value that has as many bits as a and b put together.
411   This is used for complex values.  Normally it appears only
412   in DECL_RTLs and during RTL generation, but not in the insn chain.  */
413DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
415/* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
416   all An to make a value.  This is an extension of CONCAT to larger
417   number of components.  Like CONCAT, it should not appear in the
418   insn chain.  Every element of the CONCATN is the same size.  */
419DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
421/* A memory location; operand is the address.  The second operand is the
422   alias set to which this MEM belongs.  We use `0' instead of `w' for this
423   field so that the field need not be specified in machine descriptions.  */
424DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
426/* Reference to an assembler label in the code for this function.
427   The operand is a CODE_LABEL found in the insn chain.  */
428DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
430/* Reference to a named label:
431   Operand 0: label name
432   Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
433   Operand 2: tree from which this symbol is derived, or null.
434   This is either a DECL node, or some kind of constant.  */
435DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
437/* The condition code register is represented, in our imagination,
438   as a register holding a value that can be compared to zero.
439   In fact, the machine has already compared them and recorded the
440   results; but instructions that look at the condition code
441   pretend to be looking at the entire value and comparing it.  */
442DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
444/* ----------------------------------------------------------------------
445   Expressions for operators in an rtl pattern
446   ---------------------------------------------------------------------- */
448/* if_then_else.  This is used in representing ordinary
449   conditional jump instructions.
450     Operand:
451     0:  condition
452     1:  then expr
453     2:  else expr */
454DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
456/* Comparison, produces a condition code result.  */
457DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
459/* plus */
462/* Operand 0 minus operand 1.  */
463DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
465/* Minus operand 0.  */
466DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
470/* Multiplication with signed saturation */
471DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
472/* Multiplication with unsigned saturation */
473DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
475/* Operand 0 divided by operand 1.  */
476DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
477/* Division with signed saturation */
478DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
479/* Division with unsigned saturation */
480DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
482/* Remainder of operand 0 divided by operand 1.  */
483DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
485/* Unsigned divide and remainder.  */
486DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
487DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
489/* Bitwise operations.  */
493DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
495/* Operand:
496     0:  value to be shifted.
497     1:  number of bits.  */
498DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
499DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
500DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
501DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
502DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
504/* Minimum and maximum values of two operands.  We need both signed and
505   unsigned forms.  (We cannot use MIN for SMIN because it conflicts
506   with a macro of the same name.)   The signed variants should be used
507   with floating point.  Further, if both operands are zeros, or if either
508   operand is NaN, then it is unspecified which of the two operands is
509   returned as the result.  */
516/* These unary operations are used to represent incrementation
517   and decrementation as they occur in memory addresses.
518   The amount of increment or decrement are not represented
519   because they can be understood from the machine-mode of the
520   containing MEM.  These operations exist in only two cases:
521   1. pushes onto the stack.
522   2. created automatically by the auto-inc-dec pass.  */
523DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
524DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
525DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
526DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
528/* These binary operations are used to represent generic address
529   side-effects in memory addresses, except for simple incrementation
530   or decrementation which use the above operations.  They are
531   created automatically by the life_analysis pass in flow.c.
532   The first operand is a REG which is used as the address.
533   The second operand is an expression that is assigned to the
534   register, either before (PRE_MODIFY) or after (POST_MODIFY)
535   evaluating the address.
536   Currently, the compiler can only handle second operands of the
537   form (plus (reg) (reg)) and (plus (reg) (const_int)), where
538   the first operand of the PLUS has to be the same register as
539   the first operand of the *_MODIFY.  */
540DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
541DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
543/* Comparison operations.  The ordered comparisons exist in two
544   flavors, signed and unsigned.  */
547DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
548DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
549DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
550DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
551DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
552DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
553DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
554DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
556/* Additional floating point unordered comparison flavors.  */
560/* These are equivalent to unordered or ...  */
562DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
563DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
564DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
565DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
567/* This is an ordered NE, ie !UNEQ, ie false for NaN.  */
570/* Represents the result of sign-extending the sole operand.
571   The machine modes of the operand and of the SIGN_EXTEND expression
572   determine how much sign-extension is going on.  */
573DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
575/* Similar for zero-extension (such as unsigned short to int).  */
576DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
578/* Similar but here the operand has a wider mode.  */
579DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
581/* Similar for extending floating-point values (such as SFmode to DFmode).  */
582DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
583DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
585/* Conversion of fixed point operand to floating point value.  */
586DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
588/* With fixed-point machine mode:
589   Conversion of floating point operand to fixed point value.
590   Value is defined only when the operand's value is an integer.
591   With floating-point machine mode (and operand with same mode):
592   Operand is rounded toward zero to produce an integer value
593   represented in floating point.  */
594DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
596/* Conversion of unsigned fixed point operand to floating point value.  */
597DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
599/* With fixed-point machine mode:
600   Conversion of floating point operand to *unsigned* fixed point value.
601   Value is defined only when the operand's value is an integer.  */
602DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
604/* Conversions involving fractional fixed-point types without saturation,
605   including:
606     fractional to fractional (of different precision),
607     signed integer to fractional,
608     fractional to signed integer,
609     floating point to fractional,
610     fractional to floating point.
611   NOTE: fractional can be either signed or unsigned for conversions.  */
612DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
614/* Conversions involving fractional fixed-point types and unsigned integer
615   without saturation, including:
616     unsigned integer to fractional,
617     fractional to unsigned integer.
618   NOTE: fractional can be either signed or unsigned for conversions.  */
619DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
621/* Conversions involving fractional fixed-point types with saturation,
622   including:
623     fractional to fractional (of different precision),
624     signed integer to fractional,
625     floating point to fractional.
626   NOTE: fractional can be either signed or unsigned for conversions.  */
627DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
629/* Conversions involving fractional fixed-point types and unsigned integer
630   with saturation, including:
631     unsigned integer to fractional.
632   NOTE: fractional can be either signed or unsigned for conversions.  */
633DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
635/* Absolute value */
636DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
638/* Square root */
639DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
641/* Swap bytes.  */
642DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
644/* Find first bit that is set.
645   Value is 1 + number of trailing zeros in the arg.,
646   or 0 if arg is 0.  */
647DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
649/* Count number of leading redundant sign bits (number of leading
650   sign bits minus one).  */
651DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY)
653/* Count leading zeros.  */
654DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
656/* Count trailing zeros.  */
657DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
659/* Population count (number of 1 bits).  */
660DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
662/* Population parity (number of 1 bits modulo 2).  */
663DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
665/* Reference to a signed bit-field of specified size and position.
666   Operand 0 is the memory unit (usually SImode or QImode) which
667   contains the field's first bit.  Operand 1 is the width, in bits.
668   Operand 2 is the number of bits in the memory unit before the
669   first bit of this field.
670   If BITS_BIG_ENDIAN is defined, the first bit is the msb and
671   operand 2 counts from the msb of the memory unit.
672   Otherwise, the first bit is the lsb and operand 2 counts from
673   the lsb of the memory unit.
674   This kind of expression can not appear as an lvalue in RTL.  */
675DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
677/* Similar for unsigned bit-field.
678   But note!  This kind of expression _can_ appear as an lvalue.  */
679DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
681/* For RISC machines.  These save memory when splitting insns.  */
683/* HIGH are the high-order bits of a constant expression.  */
686/* LO_SUM is the sum of a register and the low-order bits
687   of a constant expression.  */
688DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
690/* Describes a merge operation between two vector values.
691   Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
692   that specifies where the parts of the result are taken from.  Set bits
693   indicate operand 0, clear bits indicate operand 1.  The parts are defined
694   by the mode of the vectors.  */
695DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
697/* Describes an operation that selects parts of a vector.
698   Operands 0 is the source vector, operand 1 is a PARALLEL that contains
699   a CONST_INT for each of the subparts of the result vector, giving the
700   number of the source subpart that should be stored into it.  */
701DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
703/* Describes a vector concat operation.  Operands 0 and 1 are the source
704   vectors, the result is a vector that is as long as operands 0 and 1
705   combined and is the concatenation of the two source vectors.  */
706DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
708/* Describes an operation that converts a small vector into a larger one by
709   duplicating the input values.  The output vector mode must have the same
710   submodes as the input vector mode, and the number of output parts must be
711   an integer multiple of the number of input parts.  */
712DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
714/* Addition with signed saturation */
715DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
717/* Addition with unsigned saturation */
718DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
720/* Operand 0 minus operand 1, with signed saturation.  */
721DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
723/* Negation with signed saturation.  */
724DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
725/* Negation with unsigned saturation.  */
726DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
728/* Absolute value with signed saturation.  */
729DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
731/* Shift left with signed saturation.  */
732DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
734/* Shift left with unsigned saturation.  */
735DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
737/* Operand 0 minus operand 1, with unsigned saturation.  */
738DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
740/* Signed saturating truncate.  */
741DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
743/* Unsigned saturating truncate.  */
744DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
746/* Floating point multiply/add combined instruction.  */
747DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY)
749/* Information about the variable and its location.  */
750/* Changed 'te' to 'tei'; the 'i' field is for recording
751   initialization status of variables.  */
752DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA)
754/* Used in VAR_LOCATION for a pointer to a decl that is no longer
755   addressable.  */
756DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ)
758/* Represents value that argument had on function entry.  The
759   single argument is the DECL_INCOMING_RTL of the corresponding
760   parameter.  */
761DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ)
763/* Used in VAR_LOCATION for a reference to a parameter that has
764   been optimized away completely.  */
765DEF_RTL_EXPR(DEBUG_PARAMETER_REF, "debug_parameter_ref", "t", RTX_OBJ)
767/* All expressions from this point forward appear only in machine
768   descriptions.  */
771/* Pattern-matching operators:  */
773/* Use the function named by the second arg (the string)
774   as a predicate; if matched, store the structure that was matched
775   in the operand table at index specified by the first arg (the integer).
776   If the second arg is the null string, the structure is just stored.
778   A third string argument indicates to the register allocator restrictions
779   on where the operand can be allocated.
781   If the target needs no restriction on any instruction this field should
782   be the null string.
784   The string is prepended by:
785   '=' to indicate the operand is only written to.
786   '+' to indicate the operand is both read and written to.
788   Each character in the string represents an allocable class for an operand.
789   'g' indicates the operand can be any valid class.
790   'i' indicates the operand can be immediate (in the instruction) data.
791   'r' indicates the operand can be in a register.
792   'm' indicates the operand can be in memory.
793   'o' a subset of the 'm' class.  Those memory addressing modes that
794       can be offset at compile time (have a constant added to them).
796   Other characters indicate target dependent operand classes and
797   are described in each target's machine description.
799   For instructions with more than one operand, sets of classes can be
800   separated by a comma to indicate the appropriate multi-operand constraints.
801   There must be a 1 to 1 correspondence between these sets of classes in
802   all operands for an instruction.
803   */
804DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
806/* Match a SCRATCH or a register.  When used to generate rtl, a
807   SCRATCH is generated.  As for MATCH_OPERAND, the mode specifies
808   the desired mode and the first argument is the operand number.
809   The second argument is the constraint.  */
810DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
812/* Apply a predicate, AND match recursively the operands of the rtx.
813   Operand 0 is the operand-number, as in match_operand.
814   Operand 1 is a predicate to apply (as a string, a function name).
815   Operand 2 is a vector of expressions, each of which must match
816   one subexpression of the rtx this construct is matching.  */
817DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
819/* Match a PARALLEL of arbitrary length.  The predicate is applied
820   to the PARALLEL and the initial expressions in the PARALLEL are matched.
821   Operand 0 is the operand-number, as in match_operand.
822   Operand 1 is a predicate to apply to the PARALLEL.
823   Operand 2 is a vector of expressions, each of which must match the
824   corresponding element in the PARALLEL.  */
825DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
827/* Match only something equal to what is stored in the operand table
828   at the index specified by the argument.  Use with MATCH_OPERAND.  */
829DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
831/* Match only something equal to what is stored in the operand table
832   at the index specified by the argument.  Use with MATCH_OPERATOR.  */
833DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
835/* Match only something equal to what is stored in the operand table
836   at the index specified by the argument.  Use with MATCH_PARALLEL.  */
837DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
839/* Appears only in define_predicate/define_special_predicate
840   expressions.  Evaluates true only if the operand has an RTX code
841   from the set given by the argument (a comma-separated list).  If the
842   second argument is present and nonempty, it is a sequence of digits
843   and/or letters which indicates the subexpression to test, using the
844   same syntax as genextract/genrecog's location strings: 0-9 for
845   XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
846   the result of the one before it.  */
847DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
849/* Used to inject a C conditional expression into an .md file.  It can
850   appear in a predicate definition or an attribute expression.  */
851DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
853/* Insn (and related) definitions.  */
855/* Definition of the pattern for one kind of instruction.
856   Operand:
857   0: names this instruction.
858      If the name is the null string, the instruction is in the
859      machine description just to be recognized, and will never be emitted by
860      the tree to rtl expander.
861   1: is the pattern.
862   2: is a string which is a C expression
863      giving an additional condition for recognizing this pattern.
864      A null string means no extra condition.
865   3: is the action to execute if this pattern is matched.
866      If this assembler code template starts with a * then it is a fragment of
867      C code to run to decide on a template to use.  Otherwise, it is the
868      template to use.
869   4: optionally, a vector of attributes for this insn.
870     */
871DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
873/* Definition of a peephole optimization.
874   1st operand: vector of insn patterns to match
875   2nd operand: C expression that must be true
876   3rd operand: template or C code to produce assembler output.
877   4: optionally, a vector of attributes for this insn.
879   This form is deprecated; use define_peephole2 instead.  */
880DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
882/* Definition of a split operation.
883   1st operand: insn pattern to match
884   2nd operand: C expression that must be true
885   3rd operand: vector of insn patterns to place into a SEQUENCE
886   4th operand: optionally, some C code to execute before generating the
887        insns.  This might, for example, create some RTX's and store them in
888        elements of `recog_data.operand' for use by the vector of
889        insn-patterns.
890        (`operands' is an alias here for `recog_data.operand').  */
891DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
893/* Definition of an insn and associated split.
894   This is the concatenation, with a few modifications, of a define_insn
895   and a define_split which share the same pattern.
896   Operand:
897   0: names this instruction.
898      If the name is the null string, the instruction is in the
899      machine description just to be recognized, and will never be emitted by
900      the tree to rtl expander.
901   1: is the pattern.
902   2: is a string which is a C expression
903      giving an additional condition for recognizing this pattern.
904      A null string means no extra condition.
905   3: is the action to execute if this pattern is matched.
906      If this assembler code template starts with a * then it is a fragment of
907      C code to run to decide on a template to use.  Otherwise, it is the
908      template to use.
909   4: C expression that must be true for split.  This may start with "&&"
910      in which case the split condition is the logical and of the insn
911      condition and what follows the "&&" of this operand.
912   5: vector of insn patterns to place into a SEQUENCE
913   6: optionally, some C code to execute before generating the
914        insns.  This might, for example, create some RTX's and store them in
915        elements of `recog_data.operand' for use by the vector of
916        insn-patterns.
917        (`operands' is an alias here for `recog_data.operand').
918   7: optionally, a vector of attributes for this insn.  */
919DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
921/* Definition of an RTL peephole operation.
922   Follows the same arguments as define_split.  */
923DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
925/* Define how to generate multiple insns for a standard insn name.
926   1st operand: the insn name.
927   2nd operand: vector of insn-patterns.
928        Use match_operand to substitute an element of `recog_data.operand'.
929   3rd operand: C expression that must be true for this to be available.
930        This may not test any operands.
931   4th operand: Extra C code to execute before generating the insns.
932        This might, for example, create some RTX's and store them in
933        elements of `recog_data.operand' for use by the vector of
934        insn-patterns.
935        (`operands' is an alias here for `recog_data.operand').
936   5th: optionally, a vector of attributes for this expand.  */
937DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssV", RTX_EXTRA)
939/* Define a requirement for delay slots.
940   1st operand: Condition involving insn attributes that, if true,
941                indicates that the insn requires the number of delay slots
942                shown.
943   2nd operand: Vector whose length is the three times the number of delay
944                slots required.
945                Each entry gives three conditions, each involving attributes.
946                The first must be true for an insn to occupy that delay slot
947                location.  The second is true for all insns that can be
948                annulled if the branch is true and the third is true for all
949                insns that can be annulled if the branch is false.
951   Multiple DEFINE_DELAYs may be present.  They indicate differing
952   requirements for delay slots.  */
953DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
955/* Define attribute computation for `asm' instructions.  */
956DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
958/* Definition of a conditional execution meta operation.  Automatically
959   generates new instances of DEFINE_INSN, selected by having attribute
960   "predicable" true.  The new pattern will contain a COND_EXEC and the
961   predicate at top-level.
963   Operand:
964   0: The predicate pattern.  The top-level form should match a
965      relational operator.  Operands should have only one alternative.
966   1: A C expression giving an additional condition for recognizing
967      the generated pattern.
968   2: A template or C code to produce assembler output.
969   3: A vector of attributes to append to the resulting cond_exec insn.  */
970DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "EssV", RTX_EXTRA)
972/* Definition of an operand predicate.  The difference between
974   not warn about a match_operand with no mode if it has a predicate
975   defined with DEFINE_SPECIAL_PREDICATE.
977   Operand:
978   0: The name of the predicate.
979   1: A boolean expression which computes whether or not the predicate
980      matches.  This expression can use IOR, AND, NOT, MATCH_OPERAND,
981      MATCH_CODE, and MATCH_TEST.  It must be specific enough that genrecog
982      can calculate the set of RTX codes that can possibly match.
983   2: A C function body which must return true for the predicate to match.
984      Optional.  Use this when the test is too complicated to fit into a
985      match_test expression.  */
986DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
987DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
989/* Definition of a register operand constraint.  This simply maps the
990   constraint string to a register class.
992   Operand:
993   0: The name of the constraint (often, but not always, a single letter).
994   1: A C expression which evaluates to the appropriate register class for
995      this constraint.  If this is not just a constant, it should look only
996      at -m switches and the like.
997   2: A docstring for this constraint, in Texinfo syntax; not currently
998      used, in future will be incorporated into the manual's list of
999      machine-specific operand constraints.  */
1000DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
1002/* Definition of a non-register operand constraint.  These look at the
1003   operand and decide whether it fits the constraint.
1005   DEFINE_CONSTRAINT gets no special treatment if it fails to match.
1006   It is appropriate for constant-only constraints, and most others.
1008   DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
1009   to match, if it doesn't already, by converting the operand to the form
1010   (mem (reg X)) where X is a base register.  It is suitable for constraints
1011   that describe a subset of all memory references.
1013   DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
1014   to match, if it doesn't already, by converting the operand to the form
1015   (reg X) where X is a base register.  It is suitable for constraints that
1016   describe a subset of all address references.
1018   When in doubt, use plain DEFINE_CONSTRAINT.
1020   Operand:
1021   0: The name of the constraint (often, but not always, a single letter).
1022   1: A docstring for this constraint, in Texinfo syntax; not currently
1023      used, in future will be incorporated into the manual's list of
1024      machine-specific operand constraints.
1025   2: A boolean expression which computes whether or not the constraint
1026      matches.  It should follow the same rules as a define_predicate
1027      expression, including the bit about specifying the set of RTX codes
1028      that could possibly match.  MATCH_TEST subexpressions may make use of
1029      these variables:
1030        `op'    - the RTL object defining the operand.
1031        `mode'  - the mode of `op'.
1032        `ival'  - INTVAL(op), if op is a CONST_INT.
1033        `hval'  - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
1034        `lval'  - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
1035        `rval'  - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
1036                  CONST_DOUBLE.
1037      Do not use ival/hval/lval/rval if op is not the appropriate kind of
1038      RTL object.  */
1039DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
1040DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
1041DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
1044/* Constructions for CPU pipeline description described by NDFAs.  */
1046/* (define_cpu_unit string [string]) describes cpu functional
1047   units (separated by comma).
1049   1st operand: Names of cpu functional units.
1050   2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
1052   All define_reservations, define_cpu_units, and
1053   define_query_cpu_units should have unique names which may not be
1054   "nothing".  */
1055DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1057/* (define_query_cpu_unit string [string]) describes cpu functional
1058   units analogously to define_cpu_unit.  The reservation of such
1059   units can be queried for automaton state.  */
1060DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1062/* (exclusion_set string string) means that each CPU functional unit
1063   in the first string can not be reserved simultaneously with any
1064   unit whose name is in the second string and vise versa.  CPU units
1065   in the string are separated by commas.  For example, it is useful
1066   for description CPU with fully pipelined floating point functional
1067   unit which can execute simultaneously only single floating point
1068   insns or only double floating point insns.  All CPU functional
1069   units in a set should belong to the same automaton.  */
1070DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1072/* (presence_set string string) means that each CPU functional unit in
1073   the first string can not be reserved unless at least one of pattern
1074   of units whose names are in the second string is reserved.  This is
1075   an asymmetric relation.  CPU units or unit patterns in the strings
1076   are separated by commas.  Pattern is one unit name or unit names
1077   separated by white-spaces.
1079   For example, it is useful for description that slot1 is reserved
1080   after slot0 reservation for a VLIW processor.  We could describe it
1081   by the following construction
1083      (presence_set "slot1" "slot0")
1085   Or slot1 is reserved only after slot0 and unit b0 reservation.  In
1086   this case we could write
1088      (presence_set "slot1" "slot0 b0")
1090   All CPU functional units in a set should belong to the same
1091   automaton.  */
1092DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1094/* (final_presence_set string string) is analogous to `presence_set'.
1095   The difference between them is when checking is done.  When an
1096   instruction is issued in given automaton state reflecting all
1097   current and planned unit reservations, the automaton state is
1098   changed.  The first state is a source state, the second one is a
1099   result state.  Checking for `presence_set' is done on the source
1100   state reservation, checking for `final_presence_set' is done on the
1101   result reservation.  This construction is useful to describe a
1102   reservation which is actually two subsequent reservations.  For
1103   example, if we use
1105      (presence_set "slot1" "slot0")
1107   the following insn will be never issued (because slot1 requires
1108   slot0 which is absent in the source state).
1110      (define_reservation "insn_and_nop" "slot0 + slot1")
1112   but it can be issued if we use analogous `final_presence_set'.  */
1113DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1115/* (absence_set string string) means that each CPU functional unit in
1116   the first string can be reserved only if each pattern of units
1117   whose names are in the second string is not reserved.  This is an
1118   asymmetric relation (actually exclusion set is analogous to this
1119   one but it is symmetric).  CPU units or unit patterns in the string
1120   are separated by commas.  Pattern is one unit name or unit names
1121   separated by white-spaces.
1123   For example, it is useful for description that slot0 can not be
1124   reserved after slot1 or slot2 reservation for a VLIW processor.  We
1125   could describe it by the following construction
1127      (absence_set "slot2" "slot0, slot1")
1129   Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1130   slot1 and unit b1 are reserved .  In this case we could write
1132      (absence_set "slot2" "slot0 b0, slot1 b1")
1134   All CPU functional units in a set should to belong the same
1135   automaton.  */
1136DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1138/* (final_absence_set string string) is analogous to `absence_set' but
1139   checking is done on the result (state) reservation.  See comments
1140   for `final_presence_set'.  */
1141DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1143/* (define_bypass number out_insn_names in_insn_names) names bypass
1144   with given latency (the first number) from insns given by the first
1145   string (see define_insn_reservation) into insns given by the second
1146   string.  Insn names in the strings are separated by commas.  The
1147   third operand is optional name of function which is additional
1148   guard for the bypass.  The function will get the two insns as
1149   parameters.  If the function returns zero the bypass will be
1150   ignored for this case.  Additional guard is necessary to recognize
1151   complicated bypasses, e.g. when consumer is load address.  If there
1152   are more one bypass with the same output and input insns, the
1153   chosen bypass is the first bypass with a guard in description whose
1154   guard function returns nonzero.  If there is no such bypass, then
1155   bypass without the guard function is chosen.  */
1156DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1158/* (define_automaton string) describes names of automata generated and
1159   used for pipeline hazards recognition.  The names are separated by
1160   comma.  Actually it is possibly to generate the single automaton
1161   but unfortunately it can be very large.  If we use more one
1162   automata, the summary size of the automata usually is less than the
1163   single one.  The automaton name is used in define_cpu_unit and
1164   define_query_cpu_unit.  All automata should have unique names.  */
1165DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1167/* (automata_option string) describes option for generation of
1168   automata.  Currently there are the following options:
1170   o "no-minimization" which makes no minimization of automata.  This
1171     is only worth to do when we are debugging the description and
1172     need to look more accurately at reservations of states.
1174   o "time" which means printing additional time statistics about
1175      generation of automata.
1177   o "v" which means generation of file describing the result
1178     automata.  The file has suffix `.dfa' and can be used for the
1179     description verification and debugging.
1181   o "w" which means generation of warning instead of error for
1182     non-critical errors.
1184   o "ndfa" which makes nondeterministic finite state automata.
1186   o "progress" which means output of a progress bar showing how many
1187     states were generated so far for automaton being processed.  */
1188DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1190/* (define_reservation string string) names reservation (the first
1191   string) of cpu functional units (the 2nd string).  Sometimes unit
1192   reservations for different insns contain common parts.  In such
1193   case, you can describe common part and use its name (the 1st
1194   parameter) in regular expression in define_insn_reservation.  All
1195   define_reservations, define_cpu_units, and define_query_cpu_units
1196   should have unique names which may not be "nothing".  */
1197DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1199/* (define_insn_reservation name default_latency condition regexpr)
1200   describes reservation of cpu functional units (the 3nd operand) for
1201   instruction which is selected by the condition (the 2nd parameter).
1202   The first parameter is used for output of debugging information.
1203   The reservations are described by a regular expression according
1204   the following syntax:
1206       regexp = regexp "," oneof
1207              | oneof
1209       oneof = oneof "|" allof
1210             | allof
1212       allof = allof "+" repeat
1213             | repeat
1215       repeat = element "*" number
1216              | element
1218       element = cpu_function_unit_name
1219               | reservation_name
1220               | result_name
1221               | "nothing"
1222               | "(" regexp ")"
1224       1. "," is used for describing start of the next cycle in
1225       reservation.
1227       2. "|" is used for describing the reservation described by the
1228       first regular expression *or* the reservation described by the
1229       second regular expression *or* etc.
1231       3. "+" is used for describing the reservation described by the
1232       first regular expression *and* the reservation described by the
1233       second regular expression *and* etc.
1235       4. "*" is used for convenience and simply means sequence in
1236       which the regular expression are repeated NUMBER times with
1237       cycle advancing (see ",").
1239       5. cpu functional unit name which means its reservation.
1241       6. reservation name -- see define_reservation.
1243       7. string "nothing" means no units reservation.  */
1245DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1247/* Expressions used for insn attributes.  */
1249/* Definition of an insn attribute.
1250   1st operand: name of the attribute
1251   2nd operand: comma-separated list of possible attribute values
1252   3rd operand: expression for the default value of the attribute.  */
1253DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1255/* Definition of an insn attribute that uses an existing enumerated type.
1256   1st operand: name of the attribute
1257   2nd operand: the name of the enumerated type
1258   3rd operand: expression for the default value of the attribute.  */
1259DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA)
1261/* Marker for the name of an attribute.  */
1262DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1264/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1265   in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1266   pattern.
1268   (set_attr "name" "value") is equivalent to
1269   (set (attr "name") (const_string "value"))  */
1270DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1272/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1273   specify that attribute values are to be assigned according to the
1274   alternative matched.
1276   The following three expressions are equivalent:
1278   (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1279                            (eq_attrq "alternative" "2") (const_string "a2")]
1280                           (const_string "a3")))
1281   (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1282                                 (const_string "a3")])
1283   (set_attr "att" "a1,a2,a3")
1284 */
1285DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1287/* A conditional expression true if the value of the specified attribute of
1288   the current insn equals the specified value.  The first operand is the
1289   attribute name and the second is the comparison value.  */
1290DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1292/* A special case of the above representing a set of alternatives.  The first
1293   operand is bitmap of the set, the second one is the default value.  */
1294DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1296/* A conditional expression which is true if the specified flag is
1297   true for the insn being scheduled in reorg.
1299   genattr.c defines the following flags which can be tested by
1300   (attr_flag "foo") expressions in eligible_for_delay: forward, backward.  */
1302DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1304/* General conditional. The first operand is a vector composed of pairs of
1305   expressions.  The first element of each pair is evaluated, in turn.
1306   The value of the conditional is the second expression of the first pair
1307   whose first expression evaluates nonzero.  If none of the expressions is
1308   true, the second operand will be used as the value of the conditional.  */
1309DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1311/* Definition of a pattern substitution meta operation on a DEFINE_EXPAND
1312   or a DEFINE_INSN.  Automatically generates new instances of DEFINE_INSNs
1313   that match the substitution pattern.
1315   Operand:
1316   0: The name of the substitition template.
1317   1: Input template to match to see if a substitution is applicable.
1318   2: A C expression giving an additional condition for the generated
1319      new define_expand or define_insn.
1320   3: Output tempalate to generate via substitution.
1322   Within a DEFINE_SUBST template, the meaning of some RTL expressions is
1323   different from their usual interpretation: a MATCH_OPERAND matches any
1324   expression tree with matching machine mode or with VOIDmode.  Likewise,
1325   MATCH_OP_DUP and MATCH_DUP match more liberally in a DEFINE_SUBST than
1326   in other RTL expressions.  MATCH_OPERATOR matches all common operators
1327   but also UNSPEC, UNSPEC_VOLATILE, and MATCH_OPERATORS from the input
1329DEF_RTL_EXPR(DEFINE_SUBST, "define_subst", "sEsE", RTX_EXTRA)
1331/* Substitution attribute to apply a DEFINE_SUBST to a pattern.
1333   Operand:
1334   0: The name of the subst-attribute.
1335   1: The name of the DEFINE_SUBST to be applied for this attribute.
1336   2: String to substitute for the subst-attribute name in the pattern
1337      name, for the case that the DEFINE_SUBST is not applied (i.e. the
1338      unmodified version of the pattern).
1339   3: String to substitute for the subst-attribute name in the pattern
1340      name, for the case that the DEFINE_SUBST is applied to the patten.
1342   The use of DEFINE_SUBST and DEFINE_SUBST_ATTR is explained in the
1343   GCC internals manual, under "RTL Templates Transformations".  */
1344DEF_RTL_EXPR(DEFINE_SUBST_ATTR, "define_subst_attr", "ssss", RTX_EXTRA)
1346#endif /* GENERATOR_FILE */
1349Local variables:
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