source: arduino-1-6-7/trunk/fuentes/arduino-ide-amd64/libraries/WiFi/extras/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.h @ 46

Last change on this file since 46 was 46, checked in by jrpelegrina, 4 years ago

First release to Xenial

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1/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
2
3/*This file has been prepared for Doxygen automatic documentation generation.*/
4/*! \file *********************************************************************
5 *
6 * \brief Power Manager driver.
7 *
8 *
9 * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
10 * - Supported devices:  All AVR32 devices.
11 * - AppNote:
12 *
13 * \author               Atmel Corporation: http://www.atmel.com \n
14 *                       Support and FAQ: http://support.atmel.no/
15 *
16 *****************************************************************************/
17
18/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions are met:
22 *
23 * 1. Redistributions of source code must retain the above copyright notice, this
24 * list of conditions and the following disclaimer.
25 *
26 * 2. Redistributions in binary form must reproduce the above copyright notice,
27 * this list of conditions and the following disclaimer in the documentation
28 * and/or other materials provided with the distribution.
29 *
30 * 3. The name of Atmel may not be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * 4. This software may only be redistributed and used in connection with an Atmel
34 * AVR product.
35 *
36 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
37 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
38 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
39 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
40 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
41 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
42 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
43 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
45 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
46 *
47 */
48
49#ifndef _PM_H_
50#define _PM_H_
51
52#include <avr32/io.h>
53#include "compiler.h"
54#include "preprocessor.h"
55
56
57/*! \brief Sets the MCU in the specified sleep mode.
58 *
59 * \param mode Sleep mode:
60 *   \arg \c AVR32_PM_SMODE_IDLE: Idle;
61 *   \arg \c AVR32_PM_SMODE_FROZEN: Frozen;
62 *   \arg \c AVR32_PM_SMODE_STANDBY: Standby;
63 *   \arg \c AVR32_PM_SMODE_STOP: Stop;
64 *   \arg \c AVR32_PM_SMODE_DEEP_STOP: DeepStop;
65 *   \arg \c AVR32_PM_SMODE_STATIC: Static.
66 */
67#define SLEEP(mode)   {__asm__ __volatile__ ("sleep "STRINGZ(mode));}
68
69
70//! Input and output parameters when initializing PM clocks using pm_configure_clocks().
71typedef struct
72{
73  //! CPU frequency (input/output argument).
74  unsigned long cpu_f;
75
76  //! PBA frequency (input/output argument).
77  unsigned long pba_f;
78
79  //! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument).
80  unsigned long osc0_f;
81
82  //! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).
83  unsigned long osc0_startup;
84} pm_freq_param_t;
85
86#define PM_FREQ_STATUS_FAIL   (-1)
87#define PM_FREQ_STATUS_OK     (0)
88
89
90/*! \brief Gets the MCU reset cause.
91 *
92 * \param pm Base address of the Power Manager instance (i.e. &AVR32_PM).
93 *
94 * \return The MCU reset cause which can be masked with the
95 *         \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.
96 */
97#if (defined __GNUC__)
98__attribute__((__always_inline__))
99#endif
100extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)
101{
102  return pm->rcause;
103}
104
105
106/*!
107 * \brief This function will enable the external clock mode of the oscillator 0.
108 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
109 */
110extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm);
111
112
113/*!
114 * \brief This function will enable the crystal mode of the oscillator 0.
115 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
116 * \param fosc0 Oscillator 0 crystal frequency (Hz)
117 */
118extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0);
119
120
121/*!
122 * \brief This function will enable the oscillator 0 to be used with a startup time.
123 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
124 * \param startup Clock 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
125 */
126extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup);
127
128
129/*!
130 * \brief This function will disable the oscillator 0.
131 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
132 */
133extern void pm_disable_clk0(volatile avr32_pm_t *pm);
134
135
136/*!
137 * \brief This function will enable the oscillator 0 to be used with no startup time.
138 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
139 * \param startup Clock 0 startup time, for which the function does not wait. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
140 */
141extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
142
143
144/*!
145 * \brief This function will wait until the Osc0 clock is ready.
146 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
147 */
148extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm);
149
150
151/*!
152 * \brief This function will enable the external clock mode of the oscillator 1.
153 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
154 */
155extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm);
156
157
158/*!
159 * \brief This function will enable the crystal mode of the oscillator 1.
160 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
161 * \param fosc1 Oscillator 1 crystal frequency (Hz)
162 */
163extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1);
164
165
166/*!
167 * \brief This function will enable the oscillator 1 to be used with a startup time.
168 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
169 * \param startup Clock 1 startup time. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
170 */
171extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup);
172
173
174/*!
175 * \brief This function will disable the oscillator 1.
176 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
177 */
178extern void pm_disable_clk1(volatile avr32_pm_t *pm);
179
180
181/*!
182 * \brief This function will enable the oscillator 1 to be used with no startup time.
183 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
184 * \param startup Clock 1 startup time, for which the function does not wait. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
185 */
186extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
187
188
189/*!
190 * \brief This function will wait until the Osc1 clock is ready.
191 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
192 */
193extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm);
194
195
196/*!
197 * \brief This function will enable the external clock mode of the 32-kHz oscillator.
198 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
199 */
200extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm);
201
202
203/*!
204 * \brief This function will enable the crystal mode of the 32-kHz oscillator.
205 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
206 */
207extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm);
208
209
210/*!
211 * \brief This function will enable the oscillator 32 to be used with a startup time.
212 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
213 * \param startup Clock 32 kHz startup time. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
214 */
215extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup);
216
217
218/*!
219 * \brief This function will disable the oscillator 32.
220 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
221 */
222extern void pm_disable_clk32(volatile avr32_pm_t *pm);
223
224
225/*!
226 * \brief This function will enable the oscillator 32 to be used with no startup time.
227 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
228 * \param startup Clock 32 kHz startup time, for which the function does not wait. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
229 */
230extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
231
232
233/*!
234 * \brief This function will wait until the osc32 clock is ready.
235 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
236 */
237extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm);
238
239
240/*!
241 * \brief This function will select all the power manager clocks.
242 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
243 * \param pbadiv Peripheral Bus A clock divisor enable
244 * \param pbasel Peripheral Bus A select
245 * \param pbbdiv Peripheral Bus B clock divisor enable
246 * \param pbbsel Peripheral Bus B select
247 * \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)
248 * \param hsbsel High Speed Bus select (CPU clock = HSB clock )
249 */
250extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel);
251
252
253/*!
254 * \brief This function will setup a generic clock.
255 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
256 * \param gc generic clock number (0 for gc0...)
257 * \param osc_or_pll Use OSC (=0) or PLL (=1)
258 * \param pll_osc Select Osc0/PLL0 or Osc1/PLL1
259 * \param diven Generic clock divisor enable
260 * \param div Generic clock divisor
261 */
262extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div);
263
264
265/*!
266 * \brief This function will enable a generic clock.
267 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
268 * \param gc generic clock number (0 for gc0...)
269 */
270extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc);
271
272
273/*!
274 * \brief This function will disable a generic clock.
275 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
276 * \param gc generic clock number (0 for gc0...)
277 */
278extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc);
279
280
281/*!
282 * \brief This function will setup a PLL.
283 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
284 * \param pll PLL number(0 for PLL0, 1 for PLL1)
285 * \param mul PLL MUL in the PLL formula
286 * \param div PLL DIV in the PLL formula
287 * \param osc OSC number (0 for osc0, 1 for osc1)
288 * \param lockcount PLL lockount
289 */
290extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount);
291
292
293/*!
294 * \brief This function will set a PLL option.
295 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
296 * \param pll PLL number(0 for PLL0, 1 for PLL1)
297 * \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
298 * \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
299 * \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
300 */
301extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int  pll_freq, unsigned int  pll_div2, unsigned int  pll_wbwdisable);
302
303
304/*!
305 * \brief This function will get a PLL option.
306 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
307 * \param pll PLL number(0 for PLL0, 1 for PLL1)
308 * \return       Option
309 */
310extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll);
311
312
313/*!
314 * \brief This function will enable a PLL.
315 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
316 * \param pll PLL number(0 for PLL0, 1 for PLL1)
317 */
318extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll);
319
320
321/*!
322 * \brief This function will disable a PLL.
323 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
324 * \param pll PLL number(0 for PLL0, 1 for PLL1)
325 */
326extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll);
327
328
329/*!
330 * \brief This function will wait for PLL0 locked
331 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
332 */
333extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm);
334
335
336/*!
337 * \brief This function will wait for PLL1 locked
338 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
339 */
340extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm);
341
342
343/*!
344 * \brief This function will switch the power manager main clock.
345 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
346 * \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0.
347 */
348extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock);
349
350
351/*!
352 * \brief Switch main clock to clock Osc0 (crystal mode)
353 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
354 * \param fosc0 Oscillator 0 crystal frequency (Hz)
355 * \param startup Crystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
356 */
357extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup);
358
359
360/*! \brief Enables the Brown-Out Detector interrupt.
361 *
362 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
363 */
364extern void pm_bod_enable_irq(volatile avr32_pm_t *pm);
365
366
367/*! \brief Disables the Brown-Out Detector interrupt.
368 *
369 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
370 */
371extern void pm_bod_disable_irq(volatile avr32_pm_t *pm);
372
373
374/*! \brief Clears the Brown-Out Detector interrupt flag.
375 *
376 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
377 */
378extern void pm_bod_clear_irq(volatile avr32_pm_t *pm);
379
380
381/*! \brief Gets the Brown-Out Detector interrupt flag.
382 *
383 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
384 *
385 * \retval 0 No BOD interrupt.
386 * \retval 1 BOD interrupt pending.
387 */
388extern unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm);
389
390
391/*! \brief Gets the Brown-Out Detector interrupt enable status.
392 *
393 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
394 *
395 * \retval 0 BOD interrupt disabled.
396 * \retval 1 BOD interrupt enabled.
397 */
398extern unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm);
399
400
401/*! \brief Gets the triggering threshold of the Brown-Out Detector.
402 *
403 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
404 *
405 * \return Triggering threshold of the BOD. See the electrical characteristics
406 *         in the part datasheet for actual voltage levels.
407 */
408extern unsigned long pm_bod_get_level(volatile avr32_pm_t *pm);
409
410
411/*!
412 * \brief Read the content of the PM GPLP registers
413 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
414 * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
415 *
416 * \return The content of the chosen GPLP register.
417 */
418extern unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp);
419
420
421/*!
422 * \brief Write into the PM GPLP registers
423 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
424 * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
425 * \param value Value to write
426 */
427extern void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value);
428
429
430/*! \brief Enable the clock of a module.
431 *
432 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
433 * \param module The module to clock (use one of the defines in the part-specific
434 * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
435 * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
436 *
437 * \return Status.
438 *   \retval 0  Success.
439 *   \retval <0 An error occured.
440 */
441extern long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module);
442
443/*! \brief Disable the clock of a module.
444 *
445 * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
446 * \param module The module to shut down (use one of the defines in the part-specific
447 * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
448 * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
449 *
450 * \return Status.
451 *   \retval 0  Success.
452 *   \retval <0 An error occured.
453 */
454extern long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module);
455
456
457
458/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks
459 *         according to the user wishes.
460 *
461 * This function needs some parameters stored in a pm_freq_param_t structure:
462 *  - cpu_f and pba_f are the wanted frequencies,
463 *  - osc0_f is the oscillator 0 on-board frequency (e.g. FOSC0),
464 *  - osc0_startup is the oscillator 0 startup time (e.g. OSC0_STARTUP).
465 *
466 * The function will then configure the clocks using the following rules:
467 *  - It first try to find a valid PLL frequency (the highest possible value to avoid jitter) in order
468 *    to satisfy the CPU frequency,
469 *  - It optimizes the configuration depending the various divide stages,
470 *  - Then, the PBA frequency is configured from the CPU freq.
471 *  - Note that HSB and PBB are configured with the same frequency as CPU.
472 *  - Note also that the number of wait states of the flash read accesses is automatically set-up depending
473 *    the CPU frequency. As a consequence, the application needs the FLASHC driver to compile.
474 *
475 * The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
476 *
477 * \param param    pointer on the configuration structure.
478 *
479 * \retval PM_FREQ_STATUS_OK    Mode successfully initialized.
480 * \retval PM_FREQ_STATUS_FAIL  The configuration can not be done.
481 */
482extern int pm_configure_clocks(pm_freq_param_t *param);
483
484
485/*! \brief Automatically configure the USB clock.
486 *
487 * USB clock is configured to 48MHz, using the PLL1 from the Oscillator0, assuming
488 * a 12 MHz crystal is connected to it.
489 */
490extern void pm_configure_usb_clock(void);
491
492
493#endif  // _PM_H_
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