source: grub-pc/trunk/fuentes/grub-core/kern/arm/cache_armv7.S @ 22

Last change on this file since 22 was 22, checked in by mabarracus, 4 years ago

updated version and apply net.ifnames=0 into debian/rules

File size: 2.8 KB
Line 
1/*
2 *  GRUB  --  GRand Unified Bootloader
3 *  Copyright (C) 2013  Free Software Foundation, Inc.
4 *
5 *  GRUB is free software: you can redistribute it and/or modify
6 *  it under the terms of the GNU General Public License as published by
7 *  the Free Software Foundation, either version 3 of the License, or
8 *  (at your option) any later version.
9 *
10 *  GRUB is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 *  GNU General Public License for more details.
14 *
15 *  You should have received a copy of the GNU General Public License
16 *  along with GRUB.  If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <grub/symbol.h>
20
21        .file   "cache_armv7.S"
22        .text
23        .syntax unified
24#if !defined (__thumb2__)
25        .arch   armv7a
26        .arm
27#else
28        .arch   armv7
29        .thumb
30#endif
31# define DMB    dmb
32# define DSB    dsb
33# define ISB    isb
34#define ARMV7 1
35
36        @ r0  - CLIDR
37        @ r1  - LoC
38        @ r2  - current level
39        @ r3  - num sets
40        @ r4  - num ways
41        @ r5  - current set
42        @ r6  - current way
43        @ r7  - line size
44        @ r8  - scratch
45        @ r9  - scratch
46        @ r10 - scratch
47        @ r11 - scratch
48clean_invalidate_dcache:
49        push    {r4-r12, lr}
50        mrc     p15, 1, r0, c0, c0, 1   @ Read CLIDR
51        lsr     r1, r0, #24             @ Extract LoC
52        and     r1, r1, #0x7
53
54        mov     r2, #0                  @ First level, L1
552:      and     r8, r0, #7              @ cache type at current level
56        cmp     r8, #2
57        blt     5f                      @ instruction only, or none, skip level
58
59        @ set current cache level/type (for CCSIDR read)
60        lsl     r8, r2, #1
61        mcr     p15, 2, r8, c0, c0, 0   @ Write CSSELR (level, type: data/uni)
62
63        @ read current cache information
64        mrc     p15, 1, r8, c0, c0, 0   @ Read CCSIDR
65        lsr     r3, r8, #13             @ Number of sets -1
66
67        @ Keep only 14 bits of r3
68        lsl     r3, r3, #18
69        lsr     r3, r3, #18
70
71        lsr     r4, r8, #3              @ Number of ways -1
72
73        @ Keep only 9  bits of r4
74        lsl     r4, r4, #23
75        lsr     r4, r4, #23
76
77        and     r7, r8, #7              @ log2(line size in words) - 2
78        add     r7, r7, #2              @  adjust
79        mov     r8, #1
80        lsl     r7, r8, r7              @  -> line size in words
81        lsl     r7, r7, #2              @  -> bytes
82
83        @ set loop
84        mov     r5, #0                  @ current set = 0
853:      lsl     r8, r2, #1              @ insert level
86        clz     r9, r7                  @ calculate set field offset
87        mov     r10, #31
88        sub     r9, r10, r9
89        lsl     r10, r5, r9
90        orr     r8, r8, r10             @ insert set field
91
92        @ way loop
93        @ calculate way field offset
94        mov     r6, #0                  @ current way = 0
95        add     r10, r4, #1
96        clz     r9, r10                 @ r9 = way field offset
97        add     r9, r9, #1
984:      lsl     r10, r6, r9
99        orr     r11, r8, r10            @ insert way field
100
101        @ clean and invalidate line by set/way
102        mcr     p15, 0, r11, c7, c14, 2 @ DCCISW
103
104        @ next way
105        add     r6, r6, #1
106        cmp     r6, r4
107        ble     4b
108
109        @ next set
110        add     r5, r5, #1
111        cmp     r5, r3
112        ble     3b
113
114        @ next level
1155:      lsr     r0, r0, #3              @ align next level CLIDR 'type' field
116        add     r2, r2, #1              @ increment cache level counter
117        cmp     r2, r1
118        blt     2b                      @ outer loop
119
120        @ return
1216:      DSB
122        ISB
123        pop     {r4-r12, lr}
124        bx      lr
125
126#include "cache.S"
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